Ant instruction popes? 'And' and 'Pipes', surely...would like to know what ant instruction popes are though.
Neither of the leading developers of microprocessors plans to reveal any information about their yet unknown microprocessors at the Hot Chips conference. AMD, IBM, Intel and Oracle will discuss already known chips, such as Blue Gene/Q, Bulldozer, Llano, Sandy Bridge and SPARC T4, which have already been announced.
Advanced Micro Devices intends to discuss design and architecture of its already available Fusion A-series accelerated processing unit (APU) code-named Llano as well as soon-to-be launched “high-performance and power-efficient” Bulldozer x86-64 for desktops, servers and workstations. Perhaps, at the summit on Friday AMD will also reveal exact specifications as well as well as performance estimates of the new chips.
International Business Machines will disclose more details about its 64-bit PowerPC A2 based chip with 16 cores that support 4-way simultaneous multi-threading technology. The chip is expected to become available in 2012 and power IBM’s petascale supercomputers.
Intel plans to talk about its Core i-series “Sandy Bridge”, reveal some peculiarities of its power management or maybe even unveil details about the forthcoming six-core and eight-core Sandy Bridge E/EP. Besides, Intel will also present its code-named Poulson Itanium processor that is due to be out in 2012. The Itanium "Poulson" 12-wide issue microprocessor has eight multi-threaded cores with new micro-architecture and a new version of Hyper-Threading technology, a ring-based system interface and combined 50MB cache on the die. The new chip also boasts advances in reliability, availability and serviceability (RAS) to achieve mainframe reliability and resiliency. Among the key core architecture improvements, Intel names new floating point pipeline, new data ant instruction popes, new instruction buffer and doubled max execution width (6 to 12). High speed links of the new chips allow for peak processor-to-processor bandwidth of up to 128GB/s and memory bandwidth of up to 45GB/s, according to Intel.
Oracle on Friday will reveal further peculiarities of its already announced SPARC T4 which Oracle calls “highly-threaded server-on-a-chip with native support for heterogenous computing”. The chip is projected to have eight new cores with improved per-core/per-thread performance compared to the T3 and other improvements.
Among other presenters at Hot Chips conference are ARM, Cavium, Cisco, Micron, Sea Micro, Tilera, Tensilica, Xilinx and others.