Intel Corp. has disclosed more features and peculiarities about its next-generation Itanium processor code-named Poulson at the Hot Chips conference. The company continues to remain committed to the Itanium architecture, but promises to add features of Poulson to future Intel Xeon processors.

The Itanium "Poulson" 12-wide issue microprocessor has eight multi-threaded cores with new micro-architecture and a new version of Hyper-Threading technology, a ring-based system interface and combined 50MB cache on the die. Among the key core architecture improvements, Intel names new floating point pipeline, new data ant instruction popes, new instruction buffer and doubled max execution width (6 to 12). The innovations allow Intel to increase performance per watt, increase instruction throughput and boosted RAS coverage.

There  are three key feature areas of Poulson.  The first  is Intel Instruction Reply Technology, which is a major RAS enhancement.  This is the first Intel processor with  Instruction Replay RAS capability, and it utilizes a new pipeline architecture  to expand error detection in order to capture transient errors in execution. Upon  error detection, instructions can then be re-executed from the instruction  buffer queue to automatically recover from severe errors to improve resiliency.

The same instruction buffer capability also enables the  second new feature, an improved Hyper-Threading Technology. It supports performance  enhancement with Dual Domain Multithreading support, which enables independent front and  backend pipeline execution to improve multi-thread efficiency. As EPIC  architecture is already known for its highly parallel nature, this enhancement  will help take Poulson’s overall parallelism to the next level.

Lastly, Poulson is adding new instructions in four key  areas.  First there are new Integer  operations (mpy4, mpyshl4, clz). In support of the higher parallelism and multithreading  capabilities, there is expanded Data Access Hints (mov dahr), Expanded Software  Prefetch (ifetch.count) and Thread Control (hint@priority). These new  instructions lay the foundation for the Itanium architecture to grow with  future needs.

High speed links of the new chips allow for peak processor-to-processor bandwidth of up to 128GB/s and memory bandwidth of up to 45GB/s, according to Intel.

"While Itanium customers are always interested  in coming attractions, it’s also worthwhile for Intel Xeon Server customers to  also keep an eye on the evolution of Itanium, as many features originally  introduced on Itanium  often waterfall  down to subsequent generations of Xeon CPU chips. Remember that Poulson, like the current Intel  Itanium 9300 processor shares many common platform ingredients with Xeon,  including the Intel QuickPath and scalable memory interconnects, the Intel 7500  scalable memory buffer and DDR3, and the Intel 7500 chipset," said Pauline Nist, a spokeswoman at Intel.

Intel Itanium "Poulson" chip contains 3.1 billion transistors, is made using 32nm process technology and will measure by 18.2*29.9mm, which equals to 545.8mm2 die size, which is smaller compared to previous-generation Itanium "Tukwila" that is 700mm2 large.

"As you can see, most of these features are designed to take  full advantage of the 8 core, 12-wide issue architecture by enabling the  maximum amount of parallel execution. Poulson is on track for 2012 delivery (if  you attended HP Discover you may have had a chance to actually see an active Poulson system!) and the follow-on future  Kittson processor is under development," added Ms. Nist.

Tags: Intel, Itanium, IA64, HP, HP-UX, Poulson, Kittson