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Intel Corp.'s so-called "tick-tock" model  of transitioning to new manufacturing processes and micro-architectures has proved to be very efficient in making Intel the maker of the highest-performance microprocessors. Apparently, its smaller rival Advanced Micro Devices is also plotting something similar, but a bit differently.

As it appears from AMD's documents observed by an X-bit labs reader (in the comments for this news-story), starting from Piledriver micro-architecture and going forward, AMD's Fusion accelerated processing units (chips that integrate both x86 and stream processing cores) will feature "reduced", or "early" micro-architectural feature-set, whereas central processing units (CPUs) based on new designs will feature "full" or "late" feature-set. As a result, x86 performance of the former will be lower than x86 performance of the latter.

AMD wants APUs to be released earlier than fully-fledged CPUs since they are aimed at broader segment of the market. Therefore, x86 cores of Fusion chips will sport "reduced" next-generation micro-architecture (and will fully support previous-gen features and capabilities) in order to cut their development time and reduce their die size. CPUs will come to market several months after APUs and will feature more advanced x86 cores that will support more new instructions and therefore will offer better x86 performance.

For example, only fully-fledged "late" Piledriver inside Viperfish (code-name of next-gen server/desktop die design, the successor of Orochi that powers FX and Opteron chips) will be able to execute numerous new instructions as well as will receive instructions per clock (IPC) increase. Even though reduced "early" Piledriver inside code-named Trinity APUs will be more advanced than the original Bulldozer, the x86 cores are projected to be slightly less efficient than those of the full Piledriver.

The "tick-tock"-like approach is expected to allow AMD to reduce time-to-market of its new products and ensure that innovations do not negatively affect yields. On the other hand, it will create difficulties for software makers who will have to take into account that x86 cores within one generation of APUs and CPUs are slightly different. In addition, it should be noted that AMD's "tick-tock" has nothing to do with transitions to newer process technologies and is almost completely about micro-architectures.

AMD did not comment on the news-story, but the company is projected to reveal more about its future plans at the forthcoming financial analyst day on the 2nd of February, 2012.

Tags: AMD, Piledriver, Trinity, Viperfish, Vishera, Terramar, Sepang, 32nm, Bulldozer

Discussion

Comments currently: 18
Discussion started: 01/25/12 09:06:13 PM
Latest comment: 02/01/12 03:18:55 PM
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1. 
"AMD will no longer try to compete with Intel"
4 3 [Posted by: bruce555  | Date: 01/25/12 09:06:13 PM]
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for forgot a word in there

it's "compete JUST with intel"
3 3 [Posted by: Countess  | Date: 01/26/12 04:18:23 AM]
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2. 
Even though reduced "early" Piledriver inside code-named Trinity APUs will be more advanced than the original Bulldozer, the x86 cores are projected to be slightly less efficient than those of the full Piledriver.

AMD puts new puzzles before us.
I can't understand how module design w/o L3 may be faster than the same one w/ huge L3.
How tick-tock might be in use if GF isnot interested in developing a process for AMD exclusively.
BD saga has been lasting for many years and now with just a wave of magic wand we are promised a big leap in performance.
1 3 [Posted by: Azazel  | Date: 01/26/12 04:24:54 AM]
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Global Foundries should be interested. AMD is part of it.
0 0 [Posted by: Filiprino  | Date: 01/26/12 04:29:54 AM]
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Rubbish comment to a rubbish article. Perhaps they'll do it the same way Athlon II without L3 was 97% as fast as Phenom II with L3?

Let me see if I understand correctly, Anton. You're saying that AMD's next gen chips, although faster than today's, won't be as fast as the generation after that, which is totally unacceptable. Why exactly is that bad? He11, doesn't that apply to every chip ever made?

Intel, on the other hand, gives no performance increase on ticks, and very incremental increases on tocks, which makes them better because you really feel like you're getting something new on the tocks. Do I have that right?
2 1 [Posted by: minuteman  | Date: 01/26/12 06:14:17 PM]
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Where did he say totally unacceptable? Don't get all worked up. Did you take your meds today?
0 0 [Posted by: mikato  | Date: 02/01/12 03:14:48 PM]
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3. 
Actually what AMD is doing has nothing to do with "Tick Tock". They are segmenting the market due to their new APUs. Their APUs established a new market segment that never existed before. Now they want to go to the next step which is to offer desktop APUs that meet most consumer's needs but are not as expensive or as powerful as top-of-the-line discrete CPUs. Using similar but different micro code is a good means to adjust performance.

This makes perfect sense because within a few years ~80% of desktop users will be perfectly happy with an AMD desktop APU that provides excellent system performance at a lower price than a discrete CPU and GPU. Discrete desktop CPU and GPUs will remain primarily for enthusiasts who demand the most extreme performance.

AMD is also positioning their APUs for use in servers because it turns out that they provide an extremely good value/performance proposition - though Llano was never originally intended for servers. Basically AMD is changing the course of PC history with better products such as APUs that consume less power, deliver better performance and cost less than discrete CPU/GPU packages.That works for me.
12 3 [Posted by: beenthere  | Date: 01/26/12 08:18:46 AM]
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While I agree with you, I am more excited about how this will affect the performance segment.

It is nice to see the AMD is trying to learn from their mistakes and is instead trying to be upfront about the reduced feature set for first gen products with the hopes of capitalizing and gaining competitive advantage with their second gen steppings.

Competing head to head with Intel is neigh impossible nowadays. Cut your losses, learn from your mistakes, work with what is selling and adopt a design scheme that doesn't over hype new architectures(aka BD) and I feel the consumer market will appreciate it a lot more and hopefully yield the sales AMD wants to see in the future
2 2 [Posted by: veli05  | Date: 01/26/12 09:26:36 AM]
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This process started back before AMD purchased ATI. It's been in the making for years. It illustrates AMD's ability to think outside the box and deliver a better user experience at a lower price. Intel will be chasing AMD's APUs for the next few years as they will have no choice but to copy them.

The only real AMD mistake if you want to call it that was over-promoting Bulldozer and not getting the FX architecture sorted out and to market sooner. It wasn't for the lack of effort. GloFo didn't help either after AMD had the basic BD architecture ready. Bulldozer is a significant change and you'll see this evolve with Piledriver/Vishera and a few surprises along the way that will make consumers very happy.

This is what AMD was hinting at when they said they weren't going to compete head-to-head with Intel but instead do their own thing - which in the end has changed the PC industry for the better with C & E, Llano and Trinity APUs. AMD is just getting started with APUs.

It's all good for consumers.
8 3 [Posted by: beenthere  | Date: 01/26/12 10:38:35 AM]
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While I agree with you, I am more excited about how this will affect the performance segment.

It is nice to see the AMD is trying to learn from their mistakes and is instead trying to be upfront about the reduced feature set for first gen products with the hopes of capitalizing and gaining competitive advantage with their second gen steppings.

Competing head to head with Intel is neigh impossible nowadays. Cut your losses, learn from your mistakes, work with what is selling and adopt a design scheme that doesn't over hype new architectures(aka BD) and I feel the consumer market will appreciate it a lot more and hopefully yield the sales AMD wants to see in the future
2 2 [Posted by: veli05  | Date: 01/26/12 10:10:24 AM]
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4. 
no comments from sernox (he's the one who fount out about this)

BTW this has absolutely nothing to do with what intel does, i thought AMD will do exactly what intel does
please try not to mislead readers
0 1 [Posted by: madooo12  | Date: 01/26/12 10:03:04 AM]
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The headline clearly states: tick-tock model for micro-architectures.
0 0 [Posted by: Anton  | Date: 01/26/12 01:37:37 PM]
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Except for it looks nothing like a tick-tock (at least not to me) for micro-architectures.
1 0 [Posted by: daneren2005  | Date: 01/26/12 02:12:41 PM]
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Well it isn't a tick-tock in a sense of Intel's tick-tock

APU & CPU
H2 2011 - Bulldozer (00h-0Fh) CPU Only
H1 2012 - Piledriver (10h-2Fh) APU Only
H2 2012 - Piledriver (20h-2Fh) CPU Only
H1 2013 - Steamroller (30h-3Fh) APU Only
H2 2013 - Steamroller (40h-4Fh) CPU Only
etc.

The Tick-Tock of CPU and APU architectures are decoupled from each other but both improve "Bulldozer" performance

APU:
H1 2011 - Llano not Bulldozer
H1 2012 - Trinity
H1 2013 - Kaveri

CPU:
H2 2011 - Zambezi-Interlagos-Valencia
H2 2012 - Vishera and or Komodo-Terramar-Sepang
H2 2013 - Unknown FX name-Dublin-Macau

This will lead to faster performance increases in both compute capacity and power optimization

But it seems APUs are mostly Power Optimizations
and CPUs are mostly Compute Capacity increases

For now, till the K15h SOG includes Kaveri/Dublin/Macau changes it is a safe bet AMD will continue what they have done with Trinity and Viperfish

Compute Capacity = Ability to process paralleled applications(as serial applications no longer matter, IPC is a depreciated benchmark)
Power Optimizations = Lowering of TDP and Power Consumption via integration of the NB, SB, and evolution of transistors
4 0 [Posted by: seronx  | Date: 01/26/12 10:40:57 PM]
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great, you commented
i think your comments are good
but where did you get that info.
did you read the 600+ page thing
0 0 [Posted by: madooo12  | Date: 01/27/12 06:00:20 AM]
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Some info is from the AMD K15h Software Optimization Guide pdf and some I have inferred after looking at 2010 roadmaps and listening/watching 2011 HPC discussions
0 0 [Posted by: seronx  | Date: 01/27/12 01:35:36 PM]
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well intel's model is tick-tock for micro-architectures too

tick i think is for micro-architectures and tock is for die shrinks (or the reverse)
0 0 [Posted by: madooo12  | Date: 01/27/12 05:58:26 AM]
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Right, but die shrinks don't figure into AMD's version of tick-tock at all. Therefore they occur independently and will happen on whichever (tick or tock) is best at the time.
0 0 [Posted by: mikato  | Date: 02/01/12 03:18:55 PM]
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