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AMD has said that Suresh Gopalakrishnan, had joined the company as corporate vice president and general manager of its server business, reporting to Lisa Su, senior vice president and general manager of global business units. Mr. Gopalakrishnan will replace Patrick Patla, who resigned from AMD to join Samsung server efforts.

Mr. Gopalakrishnan will lead AMD’s server business and is responsible for driving the end-to-end business execution of Opteron server solutions worldwide. Andrew Feldman, the former head of SeaMicro, will continue in his role as corporate vice president and general manager of AMD’s data center server solutions business at AMD.

“Today’s data center operators and enterprises need to reduce cost and power consumption while increasing performance, and AMD has been working hard to meet these needs with our AMD Opteron processor family and SeaMicro fabric technology. Under Suresh’s leadership, we will accelerate our disruptive server strategy by leveraging our broad IP portfolio to deliver superior products designed to offer the world’s best performance-per-dollar and power efficiency," said Ms. Su.

Tags: AMD, SeaMicro, Opteron


Comments currently: 3
Discussion started: 06/25/12 06:25:55 AM
Latest comment: 06/27/12 12:53:58 PM
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well, hope they integrate gigabit networking into their chipsets
2 0 [Posted by: madooo12  | Date: 06/25/12 06:25:55 AM]
- collapse thread

It is already integrated, since the SB850. But like with any other integrated network, you need an external PHY chip to be able to use it. However, because AMD bought the IP from broadcom, only an expensive broadcom PHY is working, hence an additional, dedicated REALTEK PCIe Gb-chip is less expensive.

Furthermore, there are the volume-contracts with Realtek or intel. The more you order, the better the price, thus you try to only have *one* PCIe-chip for all your Intel/AMD mainboards to cut down costs.

Therefore next to no desktop-board is using the integrated MAC on AMD chipsets. I have not checked the server boards.

P.S: You cannot integrated the PHY, that is some analoge device which cannot be designed in smaller processes below 65/40nm or so. Hence, you always need a PHY, hence you have to waste one PCIe lane anyways, and that lane can also be used for a fully integrated Gb-chip. Not much difference.
0 0 [Posted by: Bingle  | Date: 06/27/12 02:03:55 AM]
interesting, but I'm sure chipsets are made on much larger processes than CPUs, most are 40nm
0 0 [Posted by: madooo12  | Date: 06/27/12 12:53:58 PM]


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