ARM Holdings on Wednesday introduced its CoreLink CCN-504 cache coherent network technology with 1Tb/s bandwidth for the forthcoming many-core and heterogeneous multi-core/many-core system-on-chip solutions for enterprises and high-performance systems. The interconnection is compatible with both ARM Cortex-A15 processor architecture as well as next-gen ARMv8 64-bit architecture. ARM also revealed new memory controller for such chips.
“As the amount of data used increases exponentially over the next 10-15 years, the CoreLink CCN-504 and DMC-520 will play an important role by providing high-performance system IP solutions for many-core applications,” said Tom Cronk, deputy general manager, processor division, ARM.
CoreLink CCN-504 128-bit bus is a fully-coherent, high-performance many-core solution that supports up to 16 cores (configured as four clusters with four cores inside each one) on the same silicon die as well as up to 1Tb/s of usable bandwidth. The CoreLink CCN-504 enables system coherency in heterogeneous multi-core and multi-cluster CPU/GPU systems by enabling each processor in the system to access the other processor caches. The CoreLink CCN-504 cache coherent network includes integrated level three (L3) cache and snoop filter functions. The L3 cache, which is configurable up to 16MB, extends on-chip caching for demanding workloads and offers low latency on-chip memory for allocation and sharing of data between processors, high-speed IO interfaces and accelerators. The snoop filter removes the need for broadcast coherency messaging, further reducing latency and power. ARM plans to use CoreLink CCN on chips featuring the big.Little concept.
The CoreLink CCN-504 supports both the current-generation high-end Cortex-A15 processor and future ARMv8 processors and is the first in a family of network-based interconnect products planned by ARM. Building on the AMBA 4 ACE specification, the CoreLink CCN-504 also benefits from ARM experience in hardware-based coherency, which enables improved energy-efficiency and lower latency than software coherency. Over 8000 AMBA 4 ACE specifications have been downloaded to date.
“LSI and ARM have worked closely to drive a feature-rich on-chip interconnect that can serve as the backbone for industry-leading many-core system-on-chip devices. ARM expertise in processor and interconnect technology, guided by LSI's deep understanding of networking and compute workloads, has delivered a robust, carrier-grade interconnect that will deliver scalable, deterministic performance and quality of service for today’s most advanced networks,” said Gene Scuteri, vice president of engineering at LSI.
ARM has also unveiled the new ARM CoreLink DMC-520 dynamic memory controller that has been designed and optimized to work with the CoreLink CCN-504. The new dynamic memory controller provides a high-bandwidth interface to shared off-chip memory, such as DDR3, DDR3L and DDR4 SDRAM. It is part of an integrated ARM DDR4 interface solution incorporating ARM Artisan DDR4/3 PHY IP planned for introduction in 2013.
CoreLink CCN-504 cache coherent network is available to lead licensees now, and sampling in partner products in 2013. Calxeda, an innovative developer of SoCs the server market, and LSI, a leading designer of intelligent semiconductors that accelerate storage, mobile networking and client computing, are lead licensees for the CoreLink CCN-504 launch.
“Calxeda and ARM have been working closely to meet the demands of the datacenter since ARM's initial investment in our company in 2008, and we are beginning to see the fruits that relationship. We are already building our next generation datacenter-class solutions using this new ARM CoreLink technology, and think we will once again send shockwaves across the industry when they are announced,” said Barry Evans, co-founder and CEO of Calxeda.