And TDP is completely different thing than average power or power consumed to do some task. TDP is a value manufacturer DECIDES to use and which he limits the chip.
Only applies to complying with smaller power form factors. When its for high end systems its a function of Max junction temperature for the process used.
And K10 as it exists only because the original planned successor of K8, K9 got into so big troubles that they had to completely abandon the design. So they just quickly added L3 cache and widened the SSE unit of K8 and got a K10 out from K8.
These are sweeping statements without much truth in any of it. This is what general public assumes based on what reviews sites have theorized, these sites have very little understanding of microprocessor design. If you think K10 is just a slap of L3 and wider SSE, then you grossly misinformed. The changes are much deeper than what any of the press is informed on via marketing slides provided to them by the very same chipmaker. Those will remain trade secrets for any company on their respective architectures.
This time they understood that improving single thread performance is getting difficult, so they concentrated more on improving multi-threaded performance.
How did you know "they understood"? Again sweeping statements.
For example FMA instructions cannot be added as an aftertought, all the register file read ports and bypass networks have to be designed for it, and you cannot make them wider later without complely redesigning them and that may then completely change critical paths, pipeline balance, clustering inside the core etc.
This is gibberish, it makes no sense whatsoever.
Instructions are realized through logic, logic is formed by combination of gates, gates are formed from transistors. You can make logic to realize any instruction new or old. Its upto the design team to simulate and determine the results with said architecture to see if the gains are as much as they want or lesser than expected. There is nothing to stop FMA or any other new instructions being added to K10.
Adding such logic may or may not need changes elsewhere, and if there are changes needed they a case of how much return you get for the effort. It is always preferable to simply support the new instruction set and make the changes needed for it to work. But in most cases a more severe change maybe needed to get the best out of the new instructions.
'Network bypass' that is a term used specifically in certain specific aspects of design of certain specific logic. What were you referring to? It seems you read this term somewhere without understanding what it does.
Another misconception, register file ports need not be redesigned all the time. Infact most times you don't even touch them. Its a question of balance in returns. Port reduction methodologies have been existence for years now.
And they sacrified some single-thread performance to make the cores smaller to fit more of those.
No, this is the lack of understanding in the media who later convey their opinions to the readers who then later digest this misinformation.
The bottlenecks and issues felt in some of the single threaded applications are elsewhere in the design. Those will remain trade secret regardless of it being good or bad. Sometimes companies will not bother to correct misconceptions because that would lead them to divulging some critical info on subjects they don't want the competition to get wind of.
You don't know unless you worked in AMD if the choice in not chasing higher per core IPC was a conscious choice made by design team.
We have in industry, simulation models in pre-silicon phase once we are close to GDS generation, to accurately model the entire microarchitecture with an error margin of no more than upto 4-5%. Even before that simulation process happens, its an ongoing process that is periodically updated from the time the project was first conceived to the point of GDS out.
This is to say AMD's engineers knew exactly what to expect even before first silicon tape out.
It is not your fault. I blame this sort of misinformation on the certain review sites who misguide readers.