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Intel on Monday announced the expansion of the Intel Xeon Phi coprocessors portfolio and revealed details of the second generation of Intel Xeon Phi products code named “Knights Landing”. The new products and technologies will continue to radically increase the energy efficiency and performance of supercomputers worldwide.

Intel revealed details of its second generation Intel Xeon Phi products aimed to further increase their supercomputing capabilities. Code-named “Knights Landing”, the next generation of Intel MIC architecture-based products will be available as a coprocessor or a host processor (CPU) and manufactured using Intel's 14nm process technology featuring second generation tri-gate transistors.

As a PCIe card-based coprocessor, "Knights Landing" will handle offload workloads from the system's Intel Xeon processors and provide an upgrade path for users of current generation of coprocessors, much like it does today. However, as a host processor directly installed in the motherboard socket, it will function as a CPU and enable the next leap in compute density and performance per watt, handling all the duties of the primary processor and the specialized coprocessor at the same time. When used as a CPU, "Knights Landing" will also remove programming complexities of data transfer over PCIe, common in accelerators today.

To further boost the performance for HPC workloads, Intel will significantly increase the memory bandwidth for all "Knights Landing" products by introducing integrated on-package memory. This will allow customers to take full advantage of available compute capacity without encountering memory bandwidth bottlenecks experienced today.

"Intel is helping to blaze a path toward new innovation, discovery and competitiveness with its supercomputing vision and products. There is an insatiable demand for more computing power while also achieving new levels of power efficiency. With the current and future generations of Intel Xeon Phi coprocessors, Intel Xeon processors, Intel TrueScale fabrics and software, Intel is uniquely equipped to deliver a comprehensive solution for our customers without compromise," said Raj Hazra, vice president and general manager of technical computing group at Intel.

Intel also announced the expansion of its current generation Intel Xeon Phi coprocessors with the addition of five new products that feature various performance options, memory capacity, power efficiency and form factors that are available today. The Intel Xeon Phi coprocessor 7100 family is designed and optimized to provide the best performance and offer the highest level of features, including 61 cores clocked at 1.23GHz, 16GB of memory capacity support (double the amount previously available in accelerators or coprocessors) and over 1.2TFlops of double precision performance. The Intel Xeon Phi coprocessor 3100 family is designed for high performance per dollar value. The family features 57 cores clocked at 1.1GHz and 1TFlops of double precision performance.

Lastly, Intel added another product to the Intel Xeon Phi coprocessor 5100 family announced last year. Named the Intel Xeon Phi coprocessor 5120D, it is optimized for high-density environments with the ability to allow sockets to attach directly to a mini-board for use in blade form factors.

The worldwide high performance computing (HPC) server segment is expected to grow its annual revenue by 36 percent1 from $11 billion to $15 billion over the next four years. The dramatic increase and growth of supercomputers continues to be driven by the need to quickly compute, simulate and make more informed decisions across a range of industries. Supercomputers are used to increase the accuracy of weather predictions, help to explore more efficient energy resources, develop cures for diseases, sequence the human genome and analyze big data.

Tags: Intel, Xeon Phi, Knights Landing, MIC, x86, GPGPU

Discussion

Comments currently: 9
Discussion started: 06/17/13 01:54:33 PM
Latest comment: 06/18/13 12:23:21 PM
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1. 
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2 5 [Posted by: beenthere  | Date: 06/17/13 01:54:33 PM]
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AMD will attempt to capture Knights Landing with a large fleet. But a very smart dwarf in Intel's accounting department will build a chain to trap AMD's fleet in the bay while simultaneously burning them with magical green napalm.
0 0 [Posted by: LochDhu10yr  | Date: 06/18/13 12:23:21 PM]
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2. 
so are these knights landing going to get a faster interconnect such as the current one terabyte interconnect as found in all arm arm cortex a9 etc today so these x86 cores can finally put aside the interconnect
bottleneck
0 0 [Posted by: sanity  | Date: 06/17/13 05:38:09 PM]
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do you mean the ARM 1Tbps interconnect technology? the bi-directional ring bus inside xeon phi is said to run at 1024bit wide with bandwidth about 2.5Tbps (320GB/s)
Any links/details on the cortex A9 1TB/s interconnect? that is a tremendous achievement for a CPU that known to suffer from memory subsystem.
0 0 [Posted by: ant  | Date: 06/17/13 10:41:59 PM]
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AMD just release some specs for it's next low power server CPU, code name Berlin with an ARM Cortex A57 64bit SoC and Freedom Fabric interconnect with 1.28Tb/s bandwidth
0 0 [Posted by: Memristor  | Date: 06/18/13 05:27:25 AM]
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3. 
Phi is a very interesting part, but a gigantic bet on the status quo.

While there isn't anyone can deny that is a huge amount of CPU power, and the programming flexibility will be worth it to some, the reality of harnessing more efficient GPU platforms in an easy and tangible fashion seems looming closer and closer.

While some can argue CUDA already exists, which is absolutely true, that should branch out with HSA (from many companies, not just AMD) using OpenCL etc. While this has been a promise for years, I don't think I'm alone in believing it will be a reality in a couple years. It's clearly on the horizon.

If, or perhaps when that does come about, and they are adopted and developed into a more mature and open ecosystem, I just don't see how Phi will make sense outside an x86 niche.
0 2 [Posted by: turtle  | Date: 06/17/13 06:57:19 PM]
Reply

4. 
Phi is a very interesting part, but a gigantic bet on the status quo.

While there isn't anyone can deny that is a huge amount of CPU power, and the programming flexibility will be worth it to some, the reality of harnessing more efficient GPU platforms in an easy and tangible fashion seems looming closer and closer.

While some can argue CUDA already exists, which is absolutely true, that should branch out with HSA (from many companies, not just AMD) using OpenCL etc. While this has been a promise for years, I don't think I'm alone in believing it will be a reality in a couple years. It's clearly on the horizon.

If, or perhaps when that does come about, and they are adopted and developed into a more mature and open ecosystem, I just don't see how Phi will make sense outside an x86 niche.
0 2 [Posted by: turtle  | Date: 06/17/13 07:47:03 PM]
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- collapse thread

 
Xeon Phi could do 1TFLOPS double precision at 225W with 60cores. best CUDA today, K20X, use 2688 cores to get 1.3TFLOPS double precision, with 235W. No great power efficiency advantage here and parallellize loads over 2688cores vs over 60cores could be a day and night difference. xeon phi supports OpenCL as well.
1 0 [Posted by: ant  | Date: 06/17/13 10:35:41 PM]
Reply

5. 
OK, we need a review ASAP of those. Also, a price!!

Btw, is this any good for bitcoin mining??
0 0 [Posted by: TAViX  | Date: 06/18/13 08:00:03 AM]
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