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Intel Corp. has revealed details about its upcoming microprocessor for enterprise servers at the International Solid State Circuit Technology Conference. The chip will feature up to fifteen cores, all-new topology as well as enhanced RAS [reliability, availability, scalability] features. The new chip will sport up to 15 cores.

The new generation enterprise Xeon E7-8800v2 processor code-named “Ivy Town” for high-end machines has 15 dual-threaded 64-bit Ivy-Bridge cores and 37.5MB shared L3 cache. The system interface includes two on-chip DDR3 memory controllers each with two memory channels (which support 800MT/s – 1867MT/s effective frequencies for traditional DDR3 modules as well as up to 2667MT/s speeds to connect to a memory extension buffer using voltage-mode single-ended (VMSE) interface) and supports multiple system topologies.

The Ivy Town processor’s high-speed serial I/O’s includes of 40 lanes of PCI Express (2.5/5.0/8.0Gbps), four lanes of direct media interface (DMI) (2.5/5.0Gbps), and 60 lanes of QPI (6.4/7.2/8.0Gbps) interface to connect with other central processing units (CPUs).

The floorplan of the Ivy Town chip is considerably different compared to today’s multi-core chips and is driven by the ring bus routability and latency, as well as the chop requirements to different core counts. The cores and associated L3 cache are organized in columns of five with the ring bus segment embedded. The fully populated die has 15-cores in three columns, but the die can be easily re-configured to create central processing units with lower core counts. For example, the 10-core chop removes the rightmost 3rd column and its dedicated top and bottom I/Os. Since CMOS muxes embedded in the ring bus are programmed to operate in a 2 or 3 columns configuration respectively. The 6-core chop removes the 2nd and 4th rows from the 10-core die.

The processor includes 4.31 billion transistors and is manufactured using 22nm process technology. The design supports a wide array of product offerings with thermal design power ranging from 40 to 150W and frequencies ranging from 1.4 to 3.8GHz.

To to put 15 cores into 140W thermal design envelope, Intel had to implement various measures to cut general power consumption of the chip and decrease power leakage. The “Ivytown” design uses lower-leakage transistors in non-timing-critical paths, achieving 63% usage in the cores and over 90% in the non-core area. Overall, leakage accounts for about 22% of the total power at the typical process corner, quite impressive for a multi-core chip with relatively high frequency.

The “Ivy Town” processor fits into the LGA2011 form-factors, so it can possibly fit into existing Xeon E7 machines. Intel has not proclaimed when and whether the Ivytown will be released, but if it makes it to the market, this will likely happen this year.

Intel Xeon “Ivy Town” E7-8800v2 will ne available in LGA2011 packaging and will be released shortly.

Tags: Intel, Xeon, Ivy Town, Ivytown, Ivy Bridge, 22nm

Discussion

Comments currently: 14
Discussion started: 02/16/14 05:30:52 AM
Latest comment: 03/12/14 12:08:55 PM
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1. 
15 Cores/30 Threads@ 3.8 Ghz, 37,5 L3 Cache that all at 150W?
Nice Beast, want one! And its coming for LGA2011? Yeah!
1 0 [Posted by: Rollora  | Date: 02/16/14 05:30:52 AM]
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You will be able to purchase one for mere $5000 (five thousand dollars) or thereabouts.
1 0 [Posted by: Alecto  | Date: 02/16/14 11:28:36 AM]
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I really didn't expect them to be cheap "Real" Xeon never where
0 1 [Posted by: Rollora  | Date: 02/16/14 12:51:42 PM]
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While AMD was competitive Xeon prices were Ok, now it is x2.5 higher for the same niche... It's not a surprise though...
0 0 [Posted by: Gora Gorovich  | Date: 03/12/14 12:08:55 PM]
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3.8 GHz is the maximum turbo frequency. Under full load you're not going to see anywhere near this.

And 2011 pins don't mean it will be socket compatibel. If it was compatible the regular socket 2011 would have a huge amount of unused pins.
1 1 [Posted by: sanity  | Date: 02/17/14 08:08:43 AM]
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It will be socket compatible,it is still LGA2011-0 which means no wiring etc is changed.Only if it is LGA2011-3,Haswell-E(P,X) then it will be not compatible.
0 0 [Posted by: Giggity Goebbels  | Date: 03/06/14 06:47:19 AM]
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Where have you read this info? everything I've seen is that this is another flavor of 2011, not compatible with the enthusiast socket 2011.

Sadly even if it was able to be run on "enthusiast 2011", it's still going to be locked down, so it's rather pointless without overclocking for a home user - since if you're not going to overclock, you'd might as well get the server board/socket to begin with right?

The last socket that was any fun with xeons was 1366, because the board/chipset still had control over BCLK. Sadly those days are long gone for the Intel side.
0 0 [Posted by: xrror  | Date: 03/11/14 10:54:30 PM]
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2. 
the Skylake will be a tetrafecta of Quad-channel DDR4, PCI-E 4.0, SATA-Express, and QPi.
1 1 [Posted by: qubit  | Date: 02/16/14 06:42:08 AM]
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there is no such thing as quad-channel in ddr4, or triple/dual for that matter.
there is no pcie-4.0 until '18, that's what the intel guys claimed 2 weeks ago.
1 0 [Posted by: Yorgos  | Date: 02/17/14 12:32:57 PM]
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I guess you're right! i erred on the side of a quadrilateral. Three is a more stable pyramid.
0 0 [Posted by: qubit  | Date: 02/17/14 11:12:30 PM]
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When using DDR 4, You don't have "dual/triple/quad/etc" channels like DDR 2 & 3.

Instead of using multiple shared channels to link memory units with the CPU's memory controller, each DDR4 memory module has its own dedicated point-to-point connection
.

http://arstechnica.com/bu...oming-soonmaybe-too-soon/
1 0 [Posted by: p3ngwin  | Date: 02/18/14 06:22:50 AM]
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Yup. Ease up (JEDEC has done exactly that). Thats something amd tried to do ever since Barcelona with their unganged mode. This way its only easier for everybody to attend and comply to specifications instead forking it for themselves.

There's huge reason why everybody appraised dual/ multi-channel memory in the past. But with abundance of multi-core chips, good multithreading programming approach available for last 15yrs it will light up ligfe of CPU makers (if there would be any beside Intel) a bit - so they could lightweight chips inner interface abandoning requirement for insane routing for wideband buses needed to keep all that muddy torrent to properly deliver hot data all around.

Crappy old "compatibility" apps wont benefit at all from any memory upgrade, but hopefully in PTP topology they wont clog others applications hangeing in same core cluster under same memory sky.
0 0 [Posted by: OmegaHuman  | Date: 02/20/14 11:57:12 AM]
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3. 
Could this be the reason why Apple is late with deliveries?
0 0 [Posted by: tedstoy  | Date: 02/19/14 01:39:11 AM]
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4. 
0 0 [Posted by: qubit  | Date: 02/19/14 10:20:00 AM]
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