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Intel representatives said on Monday that the forthcoming dual-core IA64 microprocessors code-named Montecito will feature an innovative “arbiter” bus that manage the work of two cores on one system bus. A rather unique feature of the CPU will become its size: about one billion of transistors and 18MB of L3 cache are to be located inside the chip.

Intel’s code-named Montecito IA64 processor will be made using 90nm manufacturing technology and will be out in 2005. Currently there are no details about the core-speed of such monsters, though, it is not very important here: dual-core microprocessors should be a lot faster compared to their single-core brethrens even if the latter run at higher speed. Furthermore, 18MB of L3 cache should also help to boost performance substantially compared to the predecessors. Although some of you may tell that IBM’s Power4 chips can provide up to 32MB of L3 even now and there is nothing really interesting in the fact that Intel will implement 18MB in 2005, we should keep in mind that those 32MB of dual-core Power4 processors’ L3 are installed on mainboards and are not built-in into the chips.

The “arbiter” bus will manage how the cores collaborate between themselves, how they utilise their FSB and L3 cache. No details have been presented by Intel officials so far, but we can pre-suppose that the “arbiter” architecture will be utilised in all multiple-core CPUs from Intel that will come in future.

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