by Anton Shilov
09/24/2003 | 04:32 AM
During AMD Athlon 64 and 64 FX product launch yesterday AMD’s founder and Chairman of the Board Mr. Jerry Sanders, confirmed the company’s plans to release multi-core microprocessors in future. The former CEO of the world's second largest CPU maker did not specify any timeframes or any particular product details featuring this promising technology.
“With coherent HyperTransport, it is inevitable that we will have multiple cores on a single chip. This is a tremendous opportunity because with our architecture the scaling is far superior to anything else that's out there.”, The Register quoted Mr. Sanders.
Frankly speaking, I do not quite understand the connection between the HyperTransport technology used to connect various computer chips mounted on a PCB and a bus for connection CPU cores to each other within a microprocessor. As we know, current implementation of the HyperTransport technology only provides up to 6.40GB/s (3.20GB/s in both sides) throughput what does not seem to be enough for connection CPU cores. Either the head of the Sunnyvale, California-based chip-maker meant the next-generation of the HyperTransport technology, or wanted to say something different to what we think.
Earlier this year it transpired that Intel will develop a special “arbiter” bus that will manage the collaboration of cores inside the Montecito processor – Intel’s first IA64 CPU featuring dual-core technology. The bus will also manage utilisation of FSB and L3 cache (see February 12, 2003 news-story for more details). There are also claims that AMD K8 processors were developed with expansion to dual-core designs in mind. This means that AMD chips already have certain capabilities of such management.
AMD K8 microprocessors and based systems demonstrated impressive scalability in performance as a result of installing more CPUs into the system. It means that from theoretical point of view multi-core processors based on the K8 architecture may become extremely fast while still being quite cost-effective.
Nevertheless, multiple cores on a single chip project is not as trivial, as you might think. For instance, one of the main advantages of AMD Opteron processors over competing Intel Xeon chips is built-in memory controller supporting dual-channel PC2700 DDR SDRAM, as a result, memory bandwidth scales together with a number of CPUs in a system; in contrast, Xeon-based computers have only one dual-channel memory controller for all microprocessors, as a consequence, up to 4 chips tend to utilise one memory bus. In case of dual-core design, the same bottleneck may emerge on AMD Opteron successors, unless they have quad-channel memory controller in order to provide enough memory bandwidth for the powerful chips.
Talking about timeframes for AMD Opteron or even Athlon 64 products with two or more cores on a single chip, we should expect the former to emerge sometime in the second half of 2005 and the latter to become available in 2H 2006 at the earliest. Since Opteron processors are intended for server applications, the cost of their manufacturing is not as critical as for desktop Athlon 64 processors; hence, dual-core Opteron may be made even using 90nm technology, while the Athlon 64 CPUs should certainly transit to 65nm before gaining an additional core. Moreover, it is highly possible that the current generation of chips will not be able to boast with dual-core designs and the whole AMD’s multi-core era will be a prerogative for future generations of its microprocessors.