Intel Revamps Montecito to Integrate 24MB of Cache

The Monster to Become Bigger

by Anton Shilov
11/14/2003 | 12:37 PM

Intel Corporation on Thursday unveiled revamped specifications of its code-named Montecito processor due in 2005. As expected, the chip will have two cores, but will incorporate spectacular 24MB of L3 cache, 6MB more than it was originally estimated.

 

Intel’s code-named Montecito Itanium-series microprocessor will be made using 90nm manufacturing technology and will be out in 2005. Currently there are no details about the core-speed of such monster, though, the main milestone of this chip for Santa Clara, California-based Intel is its two cores integrated into the same processor rather than brute clock-speed, as dual-core CPU allows running more applications simultaneously without performance degradation. Furthermore, with 24MB of level-three of on-die cache memory the Montecito will show off amazing performance improvement over the company’s Madison 9M CPUs that come in 2004.

Earlier this year Intel uncovered plans to implement its special “arbiter” bus into the chip code-named Montecito to manage how the cores collaborate between themselves, how they utilise their FSB and L3 cache. No actual peculiarities of the design have been presented by Intel officials so far, but we can pre-suppose that the “arbiter” bus architecture may be utilised in all multiple-core CPUs from Intel that will come in future.

At present Intel Itanium processors integrate 32KB L1 cache, 256KB of L2 cache and up to 6MB of L3 cache. Nowadays IA64 chips use 400MHz processor system bus (PSB) to communicate with the rest components of the system. Next year Intel will provide up to 9MB of L3 cache for its microprocessors to refresh the current lineup, but since the code-named Madison 9M and Fanwood are still made using 0.13 micron process, do not expect them to gain the clock-speed significantly over the currently shipping Intel’s 64-bit products. Also next year Intel will pump up the PSB speed for its DP Fanwood CPUs to 533MHz in the last quarter of 2004.

In order to reflect the positive acceptance of IA64 architecture by the industry Lisa Graff, director of enterprise processor marketing for Intel, told Reuters: “Intel’s Itanium 2 processors, used on high-end servers, are being widely adopted by corporations, in addition to the traditional high-performance computing market typically represented by universities and research labs.”

During IDF Fall 2003, Intel’s President and Chief Operating Officer Paul Otellini said that the Montecito processor will be two or three times faster than today’s Madison CPUs coming out later this year. Furthermore, the Tanglewood processor available in 2006 or 2007 will already be ten times faster compared to this year’s most powerful IA64 processor.

In general, Intel’s IA64 roadmap for 2005 – 2007 years looks very strong, as the company uncovers details of its future 64-bit microprocessors. The next big thing after dual-core Montecito is a product code-named Tanglewood that is projected to have up to 16 cores.