by Anton Shilov
12/05/2003 | 12:04 PM
Intel Pentium 4 Extreme Edition processor at 3.40GHz will be Intel’s only Extreme Edition chip for a while, as the company does not currently have plans to make processors with L3 cache using 90nm technology next year.
<%BANNER[article]%>The Pentium 4 Extreme Edition microprocessors called as Pentium 4 XE or Pentium 4 EE by the hardware community are based on the 0.13 micron core designed for multi-processor servers called “
Instead of producing server chips using a young 90nm fabrication technology, Intel will strengthen its MP family of 32-bit microprocessors with three introductions next year. In the first quarter of 2004 the Santa Clara, California-based semiconductor manufacturer will roll-out the Xeon MP processor with 4MB of L3 cache clocked at 3.0GHz. Moreover, in order to strengthen the overall family, the company is rumored to add 2.70GHz and 2.20GHz Xeon MP chips into the lineup. The Xeon MP 3.0GHz 4M part – presumably based on the
All new Xeon MP processors are drop-in compatible with existing 4P/8P IA32 infrastructure, such as applications based on ServerWorks GC-HE, GC-LE chipsets, using 400MHz Quad Pumped Bus.
Intel has not disclosed plans to launch
Since the main feature of Intel Pentium 4 Extreme Edition processors is the large level three cache, Intel will either have to develop another way to improve performance of its highest-end desktop processors, or to wait for
One of the ways to offset the impact of internal caches on CPU performance is to pump up the processor system bus speed (PSB). Since Intel declares support for dual-channel DDR-II memory at 533MHz, the company may have an opportunity to increase its Quad Pumped Bus performance to 1066MHz over 800MHz featured by Pentium 4 “Northwood” and “Prescott” processors. However, the company has not proclaimed plans to support 1066MHz QPB by its Grantsdale and Alderwood chipsets.
To sum up, Intel will hardly be able to make something new in Extreme Edition field in 2004 and will have to overclock it Pentium 4 SSE3 “