Intel Outlines Long-Term Itanium Roadmap

IA64 Evolution Continues

by Anton Shilov
02/19/2004 | 12:58 PM

Intel is discussing the future of its EPIC 64-bit Itanium microprocessors at the ongoing Intel Developer Forum. As the time goes, more and more code-names are unveiled: Montecito, Millington, Tukwila, Dimona, Foxton and Pellston.


Despite of quite a lot of skepticism about the IA64 architecture and its future, the Itanium 2 processors are gaining momentum, according to Intel. So far about 110 thousand of IA64 central processing units have been shipped, the majority of them – around 100 thousand units – are Itanium 2 chips supplied last year. As the economy is starting to pick up, sales of high-end server chips are going to improve as well and it certainly makes sense to continue investing in the IA64 evolution for the Santa Clara, California-based chipmaker.

The Madison 9M processor with 9MB of L3 for enterprise MP servers will start at 1.50GHz – 1.70GHz, in the third quarter of 2004, a bit faster speed-bin than originally announced, according to Intel. The part will be compatible with Intel’s own E8870 chipset and infrastructure. The Fanwood processors – a less expensive flavour of Madison – with 400MHz PSB and 3MB of L3 cache are set to launch in Q3 2004 at 1.40GHz or above. The LV Fanwood chips with 400MHz will work at speeds of about 1.20GHz or so. All Fanwood microprocessors are designed to work in DP configurations are most-likely to be compatible with E8870 chipset.

Sometime in the Q4 2004 Intel is anticipated to introduce a new platform for its Fanwood processors with support for 533MHz bus and also roll-out Fanwood/533 64-bit CPUs to take advantage of the more powerful PSB. Details of these chips due to come in a year are not available at this time. According to sources, the company is not planning to push up the speed of FSB for MP CPUs at least until the Q2 2005.

Next year will be a big year for Itanium – Intel will launch the multi-core CPUs. Montecito will be Intel’s first IA64 chip with two cores and 24MB of L3 cache. In 2003 Intel uncovered plans to implement its special “arbiter” bus into the chip code-named Montecito to manage how the cores collaborate between themselves, how they utilise their processor system bus and L3 cache. No actual peculiarities of the design have been presented by Intel officials so far, but we can pre-suppose that the “arbiter” bus architecture may be utilised in all multiple-core CPUs from Intel that will come in future. Millington is a cheaper version of Montecito, probably tailored to serve 2P systems and contain less cache, LV Millington will have lower power consumption compared to the default core.

The Montecito and Millington chips will contain two new technologies: Foxton for power management and Pellston for correcting data errors in the cache, web-site reports.

Tanglewood chip is now renamed to Tukwila, though, its multi-core conception has not changed. There will also be a chip code-named Dimona, a yet another multi-core offspring of the Itanium 2. Both are anticipated for release in 2006 and later.

Although Intel is also going to supply x86 processors with 64-bit extensions for 1P, 2P and MP machines starting from Q2 2004, IA64 and IA32e families will co-exist. One of the targets Intel would like to address is to put on par the costs of Itanium and Xeon hardware sometimes in the middle of the decade. Then, customers will be free to decide which architecture to choose. Eventually, the more progressive and cost-effective architecture is likely to survive.