by Anton Shilov
05/25/2004 | 07:07 AM
Intel is on-track with the new flavour of Itanium 2 microprocessor launch in the third quarter this year. The company plans to intro the new flagship IA64 chip at 1.70GHz clock-speed and with 9MB of L3 cache, X-bit labs has learnt.
Earlier sources familiar with the roadmap of the world’s largest chipmaker did not reveal the exact core-clock of the forthcoming top-of-the-line chip code-named
Intel Itanium 2 processors with
Low-Voltage Itanium 2 Gets a Speed Boost
Santa Clara, California-based corporation is currently shipping a number of Itanium 2 flavours for 2-way applications: Itanium 2 1.40GHz with 1.5MB L3 cache, Itanium 2 1.40GHz with 3MB L3 cache, Itanium 2 1.60GHz with 3MB L3 cache as well as Low-Voltage Intel Itanium 2 processor at 1.0GHz with 1.5MB L3 cache, which consumes approximately 62W – half the power of other existing Itanium 2 processors.
Such microprocessors are suitable for technical and scientific computing systems; various clusters; entry-level, front-end enterprise systems as well as network edge and software engineering workstations.
In the Q3 2004 Intel plans to roll-out two more IA64 central processing units to boost its 2P IA64 lineup: Itanium 2 1.60GHz with 3MB L3 cache based on Fanwood core and Low-Voltage Intel Itanium 2 processor at 1.30GHz with 3MB L3. Earlier the company planned to clock the low-voltage revision of the chip at 1.20GHz.
533MHz, 667MHz Processor System Buses for Itanium 2 Ahead
Nowadays high-end Itanium 2 lineup from Intel includes 1.50GHz, 1.40GHz and 1.30GHz models with 6MB, 4MB and 3MB L3 cache respectively. All the current chips use 400MHz Quad Pumped Bus.
667MHz PSB to be introduced early next year will be the first bump for Itanium’s bus speed that is likely to give a strong increase in performance of IA64 multi-processor servers. However, even earlier Intel is expected to boost the PSB clock-rate of Itanium 2 processors designed for 2P servers: in Q4 2004 a cut-down flavour of Madison 9M, chip code-named Fanwood, will get a 533MHz Quad Pumped Bus.
667MHz will be a magic number for Intel processors designed for multi-processor servers. The company’s next-generation Xeon MP processors with Enhanced Memory 64 Technology code-named
Multi-core, Dynamic Power Management for Itanium 2 Beyond
Intel officially outlined the long-term Itanium processor roadmap in mid-February 2004, underlining the promise to bring Itanium processors with fabulous performance later during the decade.
Next year will be a big year for Itanium – Intel will launch its first 64-bit multi-core CPUs for high-end servers, something that its competitors – IBM and Sun – have been doing for a while.
Montecito will be Intel’s first IA64 chip with two cores and 24MB of L3 cache. In 2003 Intel uncovered plans to implement its special “arbiter” bus into the chip code-named Montecito to manage how the cores collaborate between themselves, how they utilise their processor system bus and the L3 cache. No actual peculiarities of the design have been presented by Intel officials so far, but we can pre-suppose that the “arbiter” bus architecture may be utilised in all multiple-core CPUs from Intel that will come in future.
The Montecito and
Tukwila (formerly Tanglewood) will be Intel’s first multi-core IA64 processor with more than two cores. Eventually, there will also be a chip code-named Dimona, a yet another multi-core offspring of the Itanium 2. Both are anticipated for release in 2006 and later.
Official representatives from Intel did not comment on the news-story.