Intel Demos Dual-Core Server Processors

IDF Showcases Dual-Core Itanium 2

by Anton Shilov
09/08/2004 | 06:13 AM

Following rival AMD with its recent demonstration of servers featuring dual-core 64-bit microprocessors, Intel Corp., the world’s largest maker of chips, demonstrated Tuesday a high-end server with dual-core IA64 processors inside, confirming that the products are on track for release next year.

 

Intel Demos Dual-Core Itanium 2 “Montecito” Servers

During his keynote, Paul Otellini, Intel’s President, said that the industry is moving towards multi-core processors from typical increase in core-clocks. Intel promised to ship dual-core products into each of the today’s market segments in 2005 already. In 2006 the shipments will grow and over 40% desktops, over 85% of the servers and workstations and over 70% of mobile computers will acquire dual core CPUs, X-bit labs’ Anna Filatova wrote in her IDF Day 1 coverage.

Intel demonstrated a 4-way demo system based on dual-core Montecito processors, which proved capable of running up to 16 applications at a time due to the fact that each of the Montecito cores supports Hyper-Threading technology. As an example of the practical application of a computer like that Intel showed a weather simulator program from NASA and added that with all this potential a computer like that appears 50% faster than the fastest super computer on earth right now offering the performance of 60TFlops.

Dual Core IA64 Chips, DDR2, PCI Express Ahead

Montecito will be Intel’s first IA64 chip with two cores and 24MB of L3 cache. In 2003 Intel uncovered plans to implement its special “arbiter” bus into the chip code-named Montecito to manage how the cores collaborate between themselves, how they utilise their processor system bus and the L3 cache. No actual peculiarities of the design have been presented by Intel officials so far, but we can pre-suppose that the “arbiter” bus architecture may be utilised in all multiple-core CPUs from Intel that will come in future. Millington is a cheaper version of Montecito, probably tailored to serve 2P systems and contain less cache, LV Millington will have lower power consumption compared to the default core.

The Montecito and Millington chips will contain a couple of promising technologies: Foxton for dynamic power management and Pellston for correcting data errors in the cache. Intel’s president and COO Paul Otellini recently said that the Foxton is a technology to dynamically boost speed of Itanium 2 chips, but he did not outline, whether this applies to dynamic overclocking or dynamic underclocking. Typically, overclocking is not accepted in mission-critical environments, at the same time, dynamic underclocking can help to reduce power consumption and consequently the cost of ownership.

Intel’s Itanium 2 chips with two processing engines are expected to work using 667MHz Quad Pumped Bus and will feature Intel’s new core-logic for high-end servers code-named Bayshore. The latter is expected to provide support for DDR2 memory and PCI Express interconnection, bringing the latest innovations into the server market.