Intel Set to Aggressively Ramp “Core” Micro-Architecture for Servers

by Anton Shilov
04/21/2006 | 10:31 AM

Intel Corp., the world’s leading supplier of microprocessors and platforms for servers, is set to very quickly transit its dual-processor platform to the new architecture named Core. Already in the Q3 the volume of dual-processor server platforms based on the code-named Woodcrest processors will get close to the 50% mark, according to slides that Intel recently demonstrated at Intel Developer Forum (IDF) <%BANNER[article]%>Taipei.

Intel’s code-named Bensley 2-way server platform set to be introduced shortly along with the code-named Dempsey processors will acquire a little more than 10% of Intel Xeon DP platform sales in Q2 2006, slides over HKEPC web-site claim. Already in Q3 2006 the platform will acquire over 60% of shipments, mainly because the code-named Woodcrest chips will be featured in little less than 50% of DP server platforms supplied by Intel (which means that Dempsey chips will be used in 10-15% of Xeon DP-based servers).

“Bensley platform ramps with Dempsey processor in Q2 2006 and Woodcrest processor in Q3 2006, driving a quick transition off Lindenhurst platform by Q4 2006,” a slide by Intel Corp. reads.

In Q4 2006 shipments of Intel dual-processor will consist of slightly less than 70% of Woodcrest chips and a little more than 30% of NetBurst-based processors. In Q1 2007 70% of the Intel Xeon DP market will belong to the Woodcrest, 10% will be owned by Clovertown and 20% will go to the NetBurst micro-architecture-based chips.

Two main reasons behind the aggressive transition off the NetBurst architecture to the Core architecture may be increased performance and lowered power consumption by the code-named Woodcrest processor compared to the Dempsey chip.

The new Bensley platform will be based on Intel 5000P (Blackford) and Intel 5000V (Blackford VS) chipsets that support dual-core processors, PC2-4300 FB-DIMM memory, PCI Express bus, Intel’s hyper-threading, virtualization, active management and I/O acceleration technologies. The Intel 5000P is positioned to support chips that have 667MHz or 1066MHz processor system bus, whereas the Intel 5000V is positioned to work with processors that feature 667MHz bus. Later during the year Bensley platform will be able to support code-named Woodcrest processors with 1333MHz processor system bus.

Intel’s processors code-named Conroe, Merom and Woodcrest will utilize a new micro-architecture with shorter pipeline and high performance per clock ratio. The new processors will feature 14-stages pipeline, down from 31 or more stages found in current Intel Pentium (Prescott) designs, 4-issue out-of-order execution engine as well as improved performance of the floating-point unit (FPU). Also, the new chips and platforms on their base will also feature capabilities like virtualization, LaGrande technology, x86-64 in addition to EDB, EIST and AMT2.