AMD Quad-Core Opteron, Athlon 64 Processors Details Leak

by Anton Shilov
05/03/2006 | 03:11 PM

Advanced Micro Devices has been relatively open in terms of its technology and platform roadmap, however, the firm is extremely tight-lipped about specifications or features of concrete products. Nevertheless, as web-site has published details concerning AMD’s quad-core processors be released within the next two years.

According to a part of a slide published at HKEPC web-site, there are code-named Deerhound, Greyhound, Zamora and Cadiz quad-core processors in AMD’s roadmap. Except the Greyhound, the chips are intended for dual-processor or multi-processor server as well as workstation markets.

The first quad-core chip from AMD is reported to be Deerhound, which will be intended for Socket F infrastructure and will have shared level-two cache along with dual-channel registered DDR2 memory controller. The processor is projected to emerge in the second half of 2007, around half a year later compared to arch-rival Intel Corp.’s Clovertown processor aimed at the same market segment.

AMD’s second quad-core chip is code-named Greyhound, it is reportedly designed for desktops, also sports shared level-two cache, but features DDR2/3 memory controller as well as HyperTransport 3 interface, which means that it will require a new infrastructure. The Greyhound processor is expected to arrive in the first half of 2008, about a year after Intel’s quad-core Kentsfield chip for desktops.

The Deerhound processor for high-performance servers will be reportedly succeeded by the code-named Zamora chip in the second half of 2008, which will offer shared level-three cache, FD-DIMM support and HyperTransport 3 interface. Around the same timeframe AMD is projected to release a chip code-named Cadiz, which is described similarly to Greyhound. The chip will be positioned for server and workstation segment – primarily dual-processor or single-processor machines.

Earlier it was reported based on AMD’s claims that by 2008 AMD is set to introduce its so-called Direct Connect architecture 2.0 that would improve interconnection between processors and processing engines within a chip. The new interconnection architecture would allow more than 8 processors to be connected in a single coherent memory system without the need for additional logic devices. The company plans to offer the architecture that will allow to easily build up to 32-way systems. It was also unveiled that AMD plans to commercially launch quad-core chips, Hyper-Transport 3.0 interconnection protocol, extend AMD64 instruction set, as well as add FB-DIMM support for server processors in 2007. Support of DDR3 memory in 2008 was also officially confirmed.

AMD did not comment on the news-story.