Intel Creates 80-Core Microprocessor

Intel Promises 80-Core Commercial Chips in Five Years

by Anton Shilov
09/26/2006 | 11:36 PM

Intel Corp., the world’s largest maker of x86 microprocessors, announced on Tuesday that it had created a test chip that contains 80 processing cores, which is a prototype of a chip that should deliver trillion floating-point operations-per-second (teraFLOPs) of performance. The actual commercial processors with 80 processing engines should be available in 5 years timeframe.

 

Intel Senior Fellow and chief technology officer Justin Rattner said during his keynote at Intel Developer Forum that during the next decade online software services, hosted by datacenters with more than a million servers, will allow people to access personal data, media and applications from any high-performance device to play photo-realistic games, share real-time video and do multimedia data mining.

“This new usage model will challenge the industry to deliver the one trillion floating-point operations-per-second (teraFLOPs) of performance and terabytes of bandwidth,” said Mr. Rattner.

Intel’s CTO outlined the importance of three major silicon breakthroughs. He started by revealing the first details of Intel’s tera-scale research prototype silicon, the world’s first programmable TeraFLOP processor. Containing 80 simple cores and operating at 3.10GHz, the goal of this experimental chip is to test interconnect strategies for rapidly moving terabytes of data from core to core and between cores and memory.

“When combined with our recent breakthroughs in silicon photonics, these experimental chips address the three major requirements for tera-scale computing – teraOPS of performance, terabytes-per-second of memory bandwidth, and terabits-per-second of I/O capacity,” said Rattner. “While any commercial application of these technologies is years away, it is an exciting first step in bringing tera-scale performance to PCs and servers.”

Unlike existing chip designs where hundreds of millions of transistors are uniquely arranged, this chip’s design consists of 80 tiles laid out in an 8x10 block array. Each tile includes a small core, or compute element, with a simple instruction set for processing floating-point data, but is not Intel Architecture compatible. The tile also includes a router connecting the core to an on-chip network that links all the cores to each other and gives them access to memory.