by Anton Shilov
02/14/2007 | 11:47 PM
IBM has unveiled its new embedded DRAM technology, which, it promises, will help the company to improve performance of its microprocessors by up to two times and may also improve performance of various bandwidth-demanding applications, including graphics processing units (GPUs) and other multimedia chips.
“With this breakthrough solution to the processor/memory gap, IBM is effectively doubling microprocessor performance beyond what classical scaling alone can achieve,” said Dr. Subramanian Iyer, distinguished engineer and director of 45nm technology development at IBM.
IBM’s new embedded dynamic random access memory (eDRAM) technology, designed in stress-enabled 65nm silicon-on-insulator (SOI) using deep trench, improves on-processor memory performance in about one-third the space with one-fifth the standby power of conventional SRAM (static random access memory), which allows to put higher amount of cache memory inside the chip or lower the costs of processors manufactured today.
According to IBM’s specs, the 2Mb eDRAM cell has latency of 1.5ns and power supply of 1V.
IBM’s forthcoming Power 6 processor, which does not employ IBM’s new eDRAM, will only have 8MB of cache, whereas the next-generation offerings, which will be made using 45nm process technology, will already have from 24MB to 48MB of cache, according to Mr. Iyer’s comments made in an interview with Cnet.News.com. Even though Intel’s Itanium 2 processors already employ up to 24MB of cache being produced using 90nm fabrication process, the new eDRAM technology by IBM may put the company’s chips into more favourable position.
The technology is expected to be a key feature of IBM’s 45nm microprocessor roadmap and will become available beginning in 2008. In addition to multi-core microprocessors, IBM’s new eDRAM tech is targeted at graphics in gaming, networking, and other image intensive, multimedia applications.