by Anton Shilov
05/26/2009 | 10:06 PM
Intel Corp. on Tuesday officially unwrapped its next-generation microprocessor designed for high-end multi-processor servers. The new chip not only boasts with eight processing cores with Hyper-Threading technology, but the new multi-processor (MP) server platform also features functionality traditionally found in the company’s Itanium processor family.
The new Xeon MP “Nehalem-EX” platform will substantially differ from the currently available Intel-based machines. Instead of processor system bus (PSB), the future Intel Xeon MP chips will use high-bandwidth QuickPath Interconnect (QPI) links which will enable much greater performance scalability in multi-processor environments thanks to abilities of central processing units (CPUs) to better communicate with each other. Thanks to QPI, for the first time in history Intel plans to offer its customers eight-socket platform, which is capable of processing up to 128 threads simultaneously in case of eight-core processors with HyperThreading enabled. Additional scalability options including greater sockets counts will be possible with third-party solutions.
The forthcoming Nehalem-EX will add new reliability, availability and serviceability (RAS) features traditionally found in Intel Itanium processor family, such as machine check architecture (MCA) recovery. Together with new levels of performance, both high-end processors should speed the move away from more expensive, proprietary RISC-processor based systems, Intel claims.
With new RAS capabilities for high-end enterprises, Nehalem-EX can accelerate IT adoption of Intel-based platforms over RISC-based platforms by delivering a lower total cost of ownership, higher performance, lower electricity bills and the ability to standardize on a flexible IT environment.
The new enterprise Intel Xeon processor based on code-named Nehalem micro-architecture featuring 8-cores (16-threads due to HyperThreading support), 24MB of L3 cache, 2MB L2 cache, has 2.3 billion transistors and is made using 45nm process technology. The chip that is known under Beckton code-name will have four point-to-point quick path interconnect links to connect to other processors as well as system I/O operating at up to 6.4GT/s. The forthcoming Intel Xeon MP chip will also feature capability to disable certain cores or cache domains to improve manufacturing yields. The “cache and core recovery” technology will allow Intel to disable caches or cores independently in case they are defective or because of market demands. This will allow Intel to create processors not only with eight cores out of the Beckton dies, but also make chips with sever-core, six-core, five-core or any other amount of cores that makes sense. The processor will require a new platform with LGA-1567 sockets.
The next-generation Xeon MP processors have four integrated memory controllers, but those controllers will not connect to memory modules directly, but will connect to special buffers instead. Intel has not yet fully explained the nature of its scalable memory buffer, but the brief explanation indicates that the technology is similar to FB-DIMMs with AMB put onto the mainboard. Each Xeon MP socket supports up to 16 DIMMs.
Intel will produce its Xeon MP “Nehalem” processors in late 2009 and servers on their base will be launched in 2010. Intel already has over 15 design wins from 8 OEMs with its new MP platform.