Intel to Disclose Additional Details About Westmere Processors Next Month

Intel to Talk About Westmere at Intel Developer Forum in September

by Anton Shilov
08/23/2009 | 07:57 AM

Intel Corp. said that it would disclose additional details about its next-generation microprocessors code-named Westmere next month at the Intel Developer Forum 2009. The world’s largest maker of chips is expected to reveal details about new security capabilities of the forthcoming chips.


“Where Nehalem was new chip archeticture design, Westmere is the next design being used to build processors that feature two 32nm cores with 4MB of cache that sit next to a memory controller and integrated graphics built on a separate, neighboring 45nm chip, all in one package. Westmeres will be the basis of upcoming all new Core chips (Core i3, i5, and 7) over the next few months. Westmere processors will share some of the same features that were built into Nehalem, including Hyper-Threading and Turbo Boost,” a statement by Intel reads.

The Westmere generation of chips will sport seven new instructions for accelerating encryption/decryption algorithms – 6 new instructions for AES as well as carry-less multiply instruction (PCLMULQDQ). Carry-less multiplication is an essential processing component of several cryptographic systems and standards. Hence, accelerating carry-less multiplication can significantly contribute to achieving high speed secure computing and communication. Intel names full disk encryption as one of the usage models for the new instructions added to Westmere.

The first processor – code-named Clarkdale – that belongs to the Westmere family will not be aimed at ultra high performance market. Instead, it will be designed for mainstream personal computers and will feature integrated graphics core, something not meant for high-end systems targeted at computer gamers.

Just as announced originally, Intel will start shipping its first 32nm dual-core microprocessors with 4MB of cache, Hyper-Threading, dual-channel DDR3 memory controllers and integrated graphics cores late in 2009. Since Clarkdale central processing units (CPUs) has integrated memory controller, graphics core as well as PCI Express interconnection inside, there will be no need for graphics/memory controller hub (or North Bridge) on the mainboard. Instead, the new processors will connect directly to Intel 5-series core-logic (code-named Ibexpeak platform) controller hub (PCH) that will carry hard drive controller, wired and wireless network controllers, monitor physical interfaces, PCI controller and other input/output as well as platform-related capabilities.

The code-named dual-core Clarkdale processors will be sold under different brands and will support different features: