AMD’s Bulldozer Processors to Feature Multi-Threading Technology [UPDATED]

AMD to Adopt Multi-Threading in Next-Generation Processors

by Anton Shilov
08/25/2009 | 07:32 AM

UPDATE: AMD has contacted X-bit labs claiming that it has not announced any simultaneous multi-threading technologies for Bulldozer processors. Still, there are other multi-threading implementations that may still be supported.

Advanced Micro Devices announced during Hot Chips conference that its next-generation code-named Bulldozer microprocessors will feature a multi-threading technology (SMT) which would be akin to Intel Corp.’s well-known HyperThreading.

 

AMD did not reveal many details about its multi-threading capability and only said that its Bulldozer processors would support it in 2011. Still, it is rather likely that AMD’s approach may be somewhat different compared to Intel’s HT and may even be of the same kind like Sun Microsystems’ simultaneous multi-threading feature than supports execution of four threads on one physical core.

“Bulldozer expands what has been the single-threaded nature of the AMD cores in a different fashion than Intel’s HyperThreading, said Pat Conway, a representative for AMD, reports EETimes web-site.

 

It is interesting to note that earlier AMD did not consider SMT or other multi-threading implementation to be a viable feature. However, it did admit that simultaneous multi-threading is a necessary feature of the future generations of microprocessors that significantly boosts performance.

Bulldozer is the next-generation micro-architecture and processor design developed from the ground up by AMD. In fact, Bulldozer will be the first major redesign of AMD’s processor architecture singe 2003, when the firm launched its Athlon 64/Opteron (K8) processors. It is expected that the next-generation micro-processors will offer considerably higher performance than current-generation chips. AMD Bulldozer CPUs will also feature SSE5 instruction set.

The first desktop processor in the Bulldozer family is code-named Orochi and it has more than four cores, more than 8MB of cache and supports DDR3 memory. The Orochi chip will be made using 32nm process technology and is currently due in 2011. Server processors powered by Bulldozer micro-architecture are code-named Valencia and Interlagos. Those chips will have six to eight and twelve to sixteen processing engines.