AMD Discloses Peculiarities of 32nm Llano Microprocessors

AMD Confirms Dynamic Speed Boost for 32nm SOI x86 Chips

by Anton Shilov
02/09/2010 | 11:42 AM

At the International Solid-State Circuits Conference (ISSCC) Advanced Micro Devices has disclosed peculiarities regarding its x86 microprocessors produced using 32nm silicon-on-insulator process technology with high-K metal gate (HKMG) technology. Apparently, AMD’s first Fusion chip code-named Llano will be able to dynamically scale clock-speeds of its x86 cores in order to boost performance or trim power consumption.


As reported, AMD Llano accelerated processing unit (APU) will have four x86 cores based on the current micro-architecture each of which will have 9.69mm² die size (without L2 cache), a little more than 35 million transistors (without L2 cache), 2.5W – 25W power consumption, 0.8V – 1.3V voltage and target clock-speeds at over 3.0GHz clock-speed. The clock-speeds will dynamically scale their clock-speeds and voltages within the designated thermal design power in order to boost performance when a program does not require all four processing engines or trim power consumption when there is no demand for resources.

In order to further reduce power consumption and enable all the aforementioned characteristics, AMD had to implement a number of innovations into the chip on process technology and design levels:

Interestingly, AMD has not disclosed any details regarding operation of built-in ATI Radeon HD 5000-class graphics core as well as memory controller.

AMD’s and Globalfoundries’ 32nm SOI process will use high-k metal gates, 11 copper metal layers with low-k dielectric, silicon germanium-based strained silicon to improve performance as well as second generation immersion lithography.