AMD to Redesign Memory Controller in Bulldozer Chips

AMD's Future Processors Will Feature Faster Memory Controller

by Anton Shilov
09/15/2010 | 05:48 PM

Advanced Micro Devices continues to disclose details about its forthcoming processors with Bulldozer micro-architecture. Apparently, the company plans to redesign memory controller of its new central processing units (CPUs) in order to speed up memory access.

 

"There will be enhancements to our memory controllers, things we canot talk about just yet, that we expect to help reduce the time to access memory, both locally and remotely," said John Fruehe, John Fruehe, the director of product marketing for server/workstation products at AMD.

In previous-generations AMD Opteron multi-processor systems it took microprocessors two hopes to reach the information located in memory banks of other CPUs, in takes just one hope for a current generation AMD Opteron processor to reach the data in others' memory banks. One of the ways to speed up memory transfers in multi-chip systems is to implement features like HyperTransport Assist, a feature that was introduced with six-core AMD Opteron. But at present it looks like AMD's next-gen processors will not only improve memory accesses to remote memory banks, but also to local memory.

AMD's current-generation Opteron processors with eight or twelve cores have quad-channel DDR3 memory controller; next year the company's high-end server chips will "grow" to sixteen cores with the same four DDR3 memory channels and maximum memory bandwidth. Moreover, desktop chips with up to eight cores will only have dual-channel DDR3 memory controllers, which may not be enough for demanding applications.

With advances in memory controllers AMD can further improve performance of its chips and avoid memory-related bottlenecks.