AMD Vows Llano Chips in the First Half of 2011

AMD Reaffirms Fusion-Llano Plans

by Anton Shilov
10/14/2010 | 09:11 PM

Advanced Micro Devices has reaffirmed plans to start production of its code-named Llano microprocessors in the first half of next year. While the sign seems to be generally good, given track-record of Llano and surrounding rumours, it is hard to make projections.

 

"Production shipments of Llano, our 32nm APU, are planned to occur in the first half of next year," said Dirk Meyer, chief executive officer of AMD, during his recent conference call with financial analysts.

Up to the middle of 2010 the Sunnyvale, California-based chip designer convinced the world that it would ship to customers code-named Llano chips with high performance x86 cores and advanced DirectX 11 graphics in late 2010. But then the company said that the 32nm SOI process technology - jointly developed by AMD, Globalfoundries, IBM, - had been too immature to produce commercial yields. Due to low yields, AMD had to delay the roll-out of code-named Llano product, as some reported, until the second half of the year 2011. Meanwhile, AMD's claim causes some optimism.

In general, the company hopes that accelerated processing units with both x86 and graphics stream processors inside them would provide it a major source for further growth.

"We expect the APUs to provide an opportunity for us to get more platform design wins and get a greater percentage of sell-outs based on the differentiated value proposition, which comes really in two forms. Number one, superior graphics performance at better price points and better power points than is available from the competition," said Mr. Meyer.

Quite a lot is known about Llano processor, which is a part of Sabine platform. As reported earlier, AMD Llano accelerated processing unit (APU) will have four x86 cores based on the current micro-architecture each of which will have 9.69mm² die size (without L2 cache), a little more than 35 million transistors (without L2 cache), 2.5W – 25W power consumption, 0.8V – 1.3V voltage and target clock-speeds at over 3.0GHz clock-speed. The cores will dynamically scale their clock-speeds and voltages within the designated thermal design power in order to boost performance when a program does not require all four processing engines or trim power consumption when there is no demand for resources. According to sources familiar with the matter, different versions of Llano processor will have thermal design power varying from 20W to 59W: high-end dual-core, triple-core and quad-core chips will have TDP between 35W and 59W; mainstream chips with two of four x86 cores will fit into 30W thermal envelope and low-power dual-core Llano chips will have 20W TDP. Llano will be made using 32nm SOI process technology.

AMD Sabine platform will also include code-named Hudson input/output controllers that will support PCI Express graphics port, 16 USB ports, USB 3.0 support (Hudson M3 only), 6 Serial ATA ports with RAID support, 1Gb Ethernet, integrated video DAC, integrated clock-generator and so on. Besides, Sabine may also feature optional Vancouver-series graphics processing units.