by Ilya Gavrichenkov
11/23/2010 | 10:09 PM
At the International Solid-State Circuits Conference (ISSCC) 2011 Advanced Micro Devices plans to reveal additional details about its code-named Bulldozer micro-architecture as well as implementations of forthcoming microprocessors on its base. Apparently, AMD's next-gen chips will be capable of working at over 3.50GHz, which is a quite high-speed, considering the fact that the central processing units (CPUs) will have up to eight cores.
During an ISSCC session on the 21st of February, AMD will describe its dual-core processor module of eight-core Bulldozer microprocessor, according to the agenda on the web-site of the conference. During another session on the 22nd of February the company will describe implementation of its 8MB unified level-three cache of Bulldozer microprocessors. The presentations will be dedicated to ways of reducing die size, power consumption as well as improvements of yields. The description of the sessions shed more light onto the characteristics of AMD's implementation of Bulldozer micro-architecture on 32nm silicon-on-insulator process technology, which is known as code-named Orochi design (Zambezi is desktop version, Valencia is server version).
Each Bulldozer dual-core CPU module with 2MB unified L2 cache contains 213 million transistors and is 30.9mm2 large. By contrast, die size of one processing engine of Llano processor (11-layer 32nm SOI, K10.5+ micro-architecture) is 9.69mm² (without L2 cache), which indicates that AMD has succeeded in minimizing elements of its new micro-architecture so to maintain small size and production cost of the novelty.
Bulldozer processor modules are designed to operate from 0.8V to 1.3V voltages at 3.50GHz+ clock-speed. It is unclear whether 3.50GHz is average clock-speed of the forthcoming Orochi processors or they will manage to work at significantly higher frequencies. Interestingly, but the level-three cache of Bulldozer may work at a clock-speed that is lower compared to the frequencies of CPU modules.
"This micro-architecture improves performance and frequency while reducing area and power over a previous AMD x86-64 CPU in the same process. The design reduces the number of gates/cycle relative to prior designs, achieving 3.5GHz+ operation," the claim by AMD reads.
The Bulldozer's 8MB L3 cache is composed of four independent 2MB sub-caches and features column-select aliasing to improve area efficiency, supply gating and floating bit lines to reduce leakage power, and centralized redundant row and column blocks to improve yield and testability. The cache operates above 2.40GHz at 1.1V. Potentially, this may be an indicator that Orochi will work asynchronously.
While presentations from ISSCC do not reveal precise peculiarities of future microprocessors, they give indicators which may reveal certain general qualities. For example, according to an ISSCC 2010 paper claims that the target CPU clock-speed of Llano, which is made using the same fabrication process as Orochi, is "higher than 3.0GHz". Indirectly this points to high-frequency/scaling design of Bulldozer.
AMD did not comment on the news-story.