by Ilya Gavrichenkov
11/23/2010 | 11:58 PM
Intel Corp. will disclose peculiarities of its next-generation Itanium processor code-named Poulson for mission-critical applications at the International Solid-State Circuits Conference (ISSCC) in February, 2011. The new chip will double the amount of IA64 cores as well as the amount of cache, but will maintain compatibility with the current Itanium 9300-series platform.
Based on the brief agenda of the ISSCC conference, at 32nm eight-core Itanium processor, which is most likely to be Poulson as Intel skips 45nm node for its central processing units (CPU) aimed at mission-critical applications, will contain 3.1 billion transistors and will measure by 18.2*29.9mm, which equals to 545.8mm2 die size. Given that Intel knows exact size of the forthcoming microprocessor, it is highly likely that the company either already has working samples of the chip or at least its digital "floor plan".
The Itanium "Poulson" 12-wide issue microprocessor will have eight multi-threaded cores, a ring-based system interface and combined 50MB cache on the die. High speed links allow for peak processor-to-processor bandwidth of up to 128GB/s and memory bandwidth of up to 45GB/s, according to Intel. As reported previously, the Poulson processor will feature a major micro-architectural change. In particular, it will feature an improved version of Hyper-Threading technology that will be capable to execute more than two (e.g., 4 or more) threads per core. Addotionally, the novelty will feature new instructions.
Intel Poulson processor is expected to arrive on the market sometimes in 2012, according to earlier plans. The chip will be succeeded with code-named Kittson CPU later this decade.