Intel Demonstrates Working Samples of MIC Products at ISC

Intel Claims to Be On Track for Exascale Supercomputers by End of Decade

by Anton Shilov
06/21/2011 | 04:58 PM

At the International Supercomputing Conference (ISC), Intel Corp. formally outlined its vision to achieve ExaFLOPS (quintillion floating point operations per second) performance levels on supercomputers by 2018. Intel plans to introduce special compute accelerators based on new MIC x86 architecture that will eventually contain tens or hundreds of cores to greatly speed up HPC applications. So far Intel has secured several partners and shared some performance numbers.


“While Intel Xeon processors are the clear architecture of choice for the current Top500 list of supercomputers, Intel is further expanding its focus on high-performance computing (HPC) by enabling the industry for the next frontier with our many integrated core (MIC) architecture for petascale and future exascale workloads. Intel is uniquely equipped with unparalleled manufacturing technologies, new architecture innovations and a familiar software programming environment that will bring us closer to this exciting exascale goal," said Kirk Skaugen, Intel corporation vice president and general manager of the data center group.

Just like its competitors from Advanced Micro Devices as well as Nvidia Corp., Intel understands that in order to build an ExaFLOPS-class supercomputer with adequate power requirements conventional central processing units (CPUs) like Intel Xeon may prove to be inefficient and devices with higher raw horsepower and explicit parallelism may be needed. One of the issues with such devices that contain loads of compute cores is that they require new programmable models, tools, compilers and so on. Intel believes that maintaining compatibility with its x86 architecture is the best way to quickly drive those special-purpose compute accelerators to the masses.

Kirk Skaugen said there is the potential for tremendous growth of the HPC market. While supercomputers from the 1980s delivered GigaFLOPS (billions of floating point operations per second) performance, today’s most powerful machines have increased this value by several million times. This, in turn, has increased the demand for processors used in supercomputing. By 2013 Intel expects the top 100 supercomputers in the world to use one million processors. By 2015 this number is expected to double, and is forecasted to reach 8 million units by the end of the decade. The performance of the TOP500 #1 system is estimated to reach 100PFLOPS in 2015 and break the barrier of 1ExaFLOPS in 2018. By the end of the decade the fastest system on Earth is forecasted to be able to provide performance of more than 4ExaFLOPS.

With this increase in performance, though, comes a significant increase in power consumption. As an example, for today’s fastest supercomputer in China, the Tianhe-1A, to achieve exascale performance, it would require more than 1.6GW of power – an amount large enough to supply electricity to 2 million homes – thus presenting an energy efficiency challenge. Intel MIC accelerators will help to solve the problem partly. Besides, Intel and its supercomputer partners will have to trim power requirements of other components.

At ISC, Intel and some of its partners including Forschungszentrum Juelich, Leibniz Supercomputing Centre (LRZ), CERN and Korea Institute of Science and Technology Information (KISTI) showed early results of their work with the “Knights Ferry” platform, a development platform for the software that relies on MIC-accelerated systems. The demonstrations showed how Intel MIC architecture delivers both performance and software programmability advantages.

“The programming model advantage of Intel MIC architecture enabled us to quickly scale our applications running on Intel Xeon processors to the Knights Ferry Software Development Platform. This workload was originally developed and optimized for Intel Xeon processors but due to the familiarity of the programming model we could optimize the code for the Intel MIC architecture within hours and also achieved over 650GFLOPS of performance," said prof. Arndt Bode of the Leibniz Supercomputing Centre.

Intel also showed server and workstation platforms from SGI, Dell, HP, IBM, Colfax and Supermicro, all of which are working with Intel to plan products based on "Knights Corner", the first commercial MIC solution with 50+ cores that will be made using 22nm process technology.

“SGI recognizes the significance of inter-processor communications, power, density and usability when architecting for exascale. The Intel MIC products will satisfy all four of these priorities, especially with their anticipated increase in compute density coupled with familiar X86 programming environment," said Eng Lim Goh, chief technology officer at SGI.

Unfortunately, during the show Intel did not demonstrate the Knights Corner (KNC) or showcased its performance estimates. Instead, the company showed up Knights Ferry (KNF)/Aubrey Isle up and running. According to Intel, eight KNF compute boards (on 2-way Intel Xeon X5690 [3.46GHz, 6 cores, 12MB L3 cache] with 24GB DDR3 RAM at 1333MHz) achieved 7TFLOPS performance in SGEMM [single precision general matrix multiply] operations, which is not a truly high result.