Gigabyte Accidentally Reveals AMD’s FX Launch Lineup, Specs

Gigabyte Officially Unveils Specifications of AMD FX Microprocessors

by Anton Shilov
09/01/2011 | 02:23 PM

Gigabyte Technology, one of the leading manufacturers of mainboard in the world, has updated BIOS for its flagship AM3+ mainboard and accidentally reveled specifications of launch lineup of AMD FX-series central processing units code-named Zambezi. The family of AMD’s top-of-the-range chips will be consist of four eight-core models, one six-core chip and one quad-core product.

 

As noticed by VR-Zone web-site, Gigabyte’s GA-990FXA-UD7 mainboard already supports all of AMD’s FX chips due to be launched in 2011 with F4 BIOS version. In generally, Gigabyte nearly officially confirmed specifications of the chips that have been published for a number of times already, so, the BIOS update brings no surprises. Just as expected, the lineup of AMD FX-series will crowned by the FX-8150 chip, will contain four FX8100-series eight-core models, one FX-6100 six-core chip and one FX-4100 quad-core product.

Meanwhile, a number of market indicators revealed this week that the highly-anticipated microprocessors based on Bulldozer micro-architecture may become available later than expected. The mass availability of next-generation high-end desktop FX-series central processing units code-named Zambezi in September is under question mark at the moment, an industrial source told X-bit labs. Other sources indicated that the desktop chips powered by Bulldozer micro-architecture will likely be launched sometimes in the fourth quarter of 2011, more than a quarter later than the company originally expected. AMD did not comment on the information.

AMD Orochi design is the company's next-generation processor for high-end desktop (Zambezi) and server (Valencia) markets. The chip will feature up to eight processing engines, but since it is based on Bulldozer micro-architecture, those cores will be packed into four modules. Every module which will have two independent integer cores (that will share fetch, decode and L2 functionality) with dedicated schedulers, one "Flex FP" floating point unit with two 128-bit FMAC pipes with one FP scheduler. The chip will have up to 8MB L2 cache, shared 8MB L3 cache, new dual-channel DDR3 memory controller and will use HyperTransport 3.1 bus. The Zambezi chips will use new AM3+ form-factor and will require brand new platforms.

AMD did not comment on the news-story.