by Anton Shilov
10/31/2011 | 11:26 PM
Advanced Micro Devices last week reiterated its plans to launch its code-named Trinity accelerated processing unit (APU) earlier than expected originally. The industry pins a lot of hopes onto Fusion Trinity chip that combines next-gen AMD micro-architecture with the company's future graphics core due to availability issues with existing A-series APU and FX-series Bulldozer chips.
"One of the first product we launch [based on the Piledriver core] will be Trinity; we have not released an official launch date yet, but it will happen [very] early in the year," said Thomas Seifert, chief financial officer of Advanced Micro Devices, during the latest conference call with financial analysts.
AMD’s second-generation code-named Trinity APU for mainstream personal computers (Comal for notebooks and Virgo for desktops) will be made using 32nm SOI HKMG process technology at Globalfoundries. The APU will feature up to four x86 cores powered by enhanced Bulldozer/Piledriver architecture, AMD Radeon HD 7000-series "Southern Islands" graphics core with DirectX 11-class graphics support, DDR3 memory controller and other improvements. The chips will be compatible with new FM2 infrastructure.
According to a slide that resembles those from AMD's presentations published by a web-site, AMD projects Trinity's Piledriver x86 cores to offer up to 20% higher performance compared to Husky x86 cores inside Llano. In addition, the newly-architected DirectX 11 graphics core will provide up to 30% higher speed in graphics applications, such as video games. The 20% speed improvement represents AMD's projections "using digital media workload" and actual performance advantage over currently available Fusion A-series "Llano" vary depending on the applications and usage models. It is unclear whether AMD used an early silicon (which it has at hands) for its projections or makes its predictions based on theoretical data.
AMD expects the new Trinity APUs to be not only faster than Llano, but also more available because of improved yields as well as because increased number of 32nm SOI/HKMG wafer starts starting from the fourth quarters.
"Clearly, we were disappointed with the execution around the yields in the 32nm space, and that occurred over a sustained period of time. [...] We are making progress and we're focused on it every single day, and we are seeing progress. But again, we are focused at a machine-by-machine levels, step by step, and trying to improve [...] our total yields across the board. [...] We have work to do in the execution space, and while we are making progress, we need to continue that progress. I think we are seeing that steady improvement and step by step, machine by machine, we will make that progress in 32nm. We will shift significantly more 32 nanometer product in the fourth quarter than we did in third quarter," Rory Read, the recently appointed chief executive officer of AMD, told the analysts.