by Anton Shilov
11/15/2011 | 04:38 PM
Intel Corp. on Tuesday demonstrated its code-named "Knights Corner" compute accelerator for highly-parallel workloads that is made using 22nm process technology and will be Intel's first commercial product based on many integrated cores (MIC) architecture. The KNC accelerator can deliver substantially higher horsepower that existing compute cards.
Intel's Knights Corner accelerator has over 50 cores and delivers 1TFLOPS of double precision floating point performance, as measured by the double-precision, general matrix-matrix multiplication benchmark (DGEMM). Currently the most powerful special purpose highly-parallel accelerator is Nvidia Tesla 2090, which boasts with 665GFLOPS (0.665TFLOPS) of peak performance, which is considerably below peak performance of Intel's KNC.
Rajeeb Hazra holding Knights Corner accelerator
The first presentation of the first silicon of “Knights Corner” co-processor showed that Intel architecture is capable of delivering more than 1TFLOPS of double precision floating point performance and this was the first demonstration of a single processing chip capable of achieving such a performance level. Interestingly, but the KNC accelerator is not just a PCI Express accelerator like its predecessor, the Knights Ferry compute accelerator for software developers, but looks like CPU that plugs into a socket or a special adapter.
“Intel first demonstrated a Teraflop supercomputer utilizing 9680 Intel Pentium Pro processors in 1997 as part of Sandia Lab’s 'ASCI RED' system. Having this performance now in a single chip based on Intel MIC architecture is a milestone that will once again be etched into HPC history,” said Rajeeb Hazra, general manager of technical computing at Intel datacenter and connected systems group.
Knights Corner, the first commercial Intel MIC architecture product, will be manufactured using Intel’s latest 3D tri-gate 22nm transistor process and will feature more than 50 cores. When available, Intel MIC products will offer both high performance from an architecture specifically designed to process highly parallel workloads, and compatibility with existing x86 programming model and tools. One of the benefits of Intel MIC architecture is the ability to run existing applications without the need to port the code to a new programming environment. This will allow scientists to use both CPU and co-processor performance simultaneously with existing x86 based applications, dramatically saving time, cost and resources that would otherwise be needed to rewrite them to alternative proprietary languages.
As previously announced at the International Supercomputing Conference 2011 in Hamburg, Germany, Intel’s goal is to deliver exascale-level performance by 2018 (which is more than 100 times faster performance than is currently available) while only requiring two times the power usage of the current top supercomputer. Fundamental to achieving that goal is working closely with the HPC community, and today Intel announced several new initiatives that will help to achieve that goal.