by Anton Shilov
12/07/2011 | 07:15 PM
Advanced Micro Devices has notified some of the product review web-sites (1, 2) that it had provided misleading transistor count number for its highly-anticipated eight-core microprocessors based on the Bulldozer micro-architecture. The reasons why AMD originally reported a wrong number of elements for its chip are completely unclear.
Based on the latest information provided by the world's second largest developer of x86 microprocessors on the planet, the eight-core chip code named Orochi - which powers the latest FX "Zambezi" product for desktops as well as Opteron "Valencia" and "Interlagos" products for servers - contains 1.2 billion transistors, not 2.0 billion as reported previously when the central processing unit was formally introduced and majority of its details disclosed.
Transistor count is an important characteristic of microprocessors as it describes their complexity and allows professionals to estimate performance and capabilities of such CPUs. The two billion of transistors was considered as incredibly high number for a chip that could barely outperform AMD's previous generation offering and lost the absolute majority of benchmarks to Intel Corp.'s Core i7-/i5-2000-series "Sandy Bridge" microprocessors released earlier this year and which feature a little less than a billion of transistors in their full-speed versions.
The corrected number of transistors - 1.2 billion - on the one hand shows that AMD has managed to squeeze eight x86 processing cores into a relatively low transistor budget, a rather remarkable achievement. But on the other hand the moderate amount of transistors prove that AMD had to sacrifice a lot to increase the core count and as a consequence its eight-core Bulldozer offerings are slower than Intel's quad-core Sandy Bridge chips.
AMD itself remained extremely tight-lipped over the reasons why it reported the wrong transistor count for its latest CPUs initially after the commercial launch. AMD publicly said at a chip conference that each Bulldozer dual-core CPU module with 2MB unified L2 cache contains 213 million transistors and is 30.9mm2 large. As a result, all four CPU modules with L2 cache within Zambezi/Orochi processor consist of 852 million of transistors and take 123.6mm2 of die space. Assuming that 8MB of L3 cache (6 bits per cell) consist of 405 million of transistors, it leaves very few transistors to various input/output interfaces, dual-channel DDR3 memory controller as well as various logic and routing inside the chip. Moreover, since official 315mm2 Orochi die size remained unchanged, it means that there are some secrets within the chip that AMD decided not to uncover.
The most logical explanation is that someone from AMD made a mistake inside the firm's marketing documents. Some suggest that the company used automatic tools to make the layout of its processors so extensively that it did not know the transistor count for sure. Other believe that the firm had to disable certain blocks of its chips of its chips because of the poor manufacturability. Yet another explanation is that AMD had to build a lot of redundant blocks, or even full cores for redundancy reasons but at least this is not something that can be seen on the Orochi die shots.