by Anton Shilov
02/22/2012 | 08:54 PM
Advanced Micro Devices disclosed at the International Solid-State Circuits Conference (ISSCC) that in order to increase clock-speeds of its forthcoming microprocessors based on Piledriver micro-architecture, it will use a new resonant clock mesh technology developed by Cyclos Semiconductor. The new tech allows to cut power consumption by 10%, or boost clock-speed by 10% without inrease of TDP.
AMD’s x86-64 core code-named “Piledriver” with 4GHz and higher clock-speeds employs resonant clocking to reduce clock distribution power up to 24% while maintaining the low clock-skew target required by high-performance processors. Fabricated in a 32nm SOI process, Piledriver represents the first volume production-enabled implementation of resonant clock mesh technology.
“We were able to seamlessly integrate the Cyclos IP into our existing clock mesh design process so there was no risk to our development schedule. Silicon results met our power reduction expectations, we incurred no increase in silicon area, and we were able to use our standard manufacturing process, so the investment and risk in adopting resonant clock mesh technology was well worth it as all of our customers are clamoring for more energy efficient processor designs,” said Samuel Naffziger, corporate fellow at AMD.
Cyclos resonant clock mesh technology employs on-chip inductors to create an electric pendulum, or “tank circuit”, formed by the large capacitance of the clock mesh in parallel with the Cyclos inductors. The Cyclos inductors and clock control circuits “recycle” the clock power instead of dissipating it on every clock cycle like in a clock tree implementation, which results in a reduction in total IC power consumption of up to 10%.
Clock mesh power reduction is one area where EDA vendors have not yet delivered design solutions so the validation of resonant clock mesh technology via the AMD Piledriver design is welcome news to the IC design community.
Implementing inductors on-chip to resonate a clock mesh is a simple idea with complex implementation requirements. Cyclos has commercialized over 10 years of research to produce the first resonant clock mesh design solution that meets all the testability, reliability, dynamic frequency scaling, and quality assurance requirements of today’s ICs.
“Now that the Cyclos technology is validated, we’re looking forward to expand into SoC designs via the design automation tools that are in development at Cyclos. We believe resonant clock mesh design will be a key enabler for GHz+ embedded processor IP blocks in next generation SoCs that also require ultra-low power consumption,” said Marios Papaefthymiou, founder and president of Cyclos Semiconductor.