by Anton Shilov
04/17/2012 | 08:52 PM
ARM Holdings on Tuesday said that the high performance, power-optimized quad-core hard macro implementation of its flagship ARM Cortex-A15 MPCore processor is now available for licensing. The interested parties can get the appropriate blueprints, add their own IP and manufacture the chips using 28nm HPM process technology at Taiwan Semiconductor Manufacturing Company.
The ARM Cortex-A15 MP4 hard macro is designed to run at 2.0GHz and deliver performance in excess of 20 000DMIPS (Dhrystone million instructions per second), while maintaining the same power consumption as the Cortex-A9 hard macro. The low leakage implementation features 2x32KB L1 and 2MB L2 caches with ECC, integrated NEON SIMD accelerators and floating point (VFP) technology, 224 interrupts, 6 power domains, AMBA domain bridge, CoreSight, APB, ATB, Funnel and so on.
ARM positions the implementation for a "wide array of high-performance computing applications", such as notebooks as well as power-efficient, extreme performance-orientated network and enterprise devices.
“For SoC designers looking to make a trade-off between the flexibility offered by the traditional RTL-based SoC development strategy and a rapid time to market, with ensured, benchmarked power, performance and area, an ARM hard macro implementation is an ideal, cost-effective solution. This new Cortex-A15 hard macro is an important addition to our portfolio and will enable a wider array of partners to leverage the outstanding capabilities of the Cortex-A15 processor,” said Jim Nicholas, vice president of marketing at processor division of ARM.
The hard macro was developed using ARM Artisan 12-track libraries and the recently announced processor optimization pac (POP) solution for the Cortex-A15 on TSMC 28nm HPM process, which will become available later this year. The Cortex-A15 hard macro development is the result of the synergy arising from the combination of ARM Cortex processor IP, Artisan physical IP, CoreLink systems IP and ARM integration capabilities.
Full configuration and implementation details will be presented at the Cool Chips conference in Yokohama, Japan. Further information is contained in an accompanying blog.