by Anton Shilov
05/24/2012 | 06:28 PM
Advanced Micro Devices will commence production of its next-generation high-performance x86 central processing units for high-end desktops and servers in the third quarter of the year, a media report claims. The new chips will improve instructions per clock performance of existing chips by at least 15%, the story claims.
AMD will start volume manufacturing of code-named Vishera microprocessors with up to eight Piledriver-class x86 cores sometimes in the third quarter of 2012, according to a news-report from Donanimhaber web-site. Although the web-site specifically notes next-generation FX-series processors known as Vishera, it is highly likely that the company will initiate production of Viperfish dies in general that will power both code-named "Vishera" FX products for desktops as well as code-named "Seoul" and "Abu Dhabi" Opteron chips for servers.
AMD recently indicated that the AMD FX "Vishera" central processing units sport up to eight Piledriver (next-generation Bulldozer) x86 cores, dual-channel DDR3 memory controller and are compatible with AM3+ infrastructure as well as Scorpius platform featuring AMD 990FX core-logic sets. Although the new platform has its own code-name "Volan", some sources refer to it as "Scorpius Refresh".
It is interesting to note that the Donanimhaber indicates that instruction per clock (IPC) performance of Vishera will be 15% higher compared to that of current-generation Zambezi thanks to Piledriver micro-architecture as well as some other tweaks. Earlier it was widely believed that FX "Vishera" chips will only bring 10% speed improvement at the same clock-speed compared to the currently available chips.
As it appears from AMD's documents revealed earlier this year, starting from Piledriver micro-architecture and going forward, AMD's Fusion accelerated processing units (chips that integrate both x86 and stream processing cores) will feature "reduced", or "early" micro-architectural feature-set, whereas central processing units based on new designs will feature "full" or "late" feature-set. As a result, x86 performance of the former will be lower than x86 performance of the latter.
For example, only fully-fledged "late" Piledriver inside Viperfish model 2xh will be able to execute numerous new instructions as well as will receive instructions per clock (IPC) increase. Even though reduced "early" Piledriver inside code-named Trinity APUs model 1xh will be more advanced than the original Bulldozer model 0xh, the x86 cores are projected to be slightly less efficient than those of the full Piledriver.
AMD did not comment on the news-story.