AMD's New Low-Power Micro-Architecture to Support AVX, BMI Other New Instructions

AMD Jaguar to Support Advanced Instructions Found on Higher-End Chips

by Anton Shilov
07/24/2012 | 01:45 PM

Current low-power microprocessors based on AMD Bobcat and Intel Bonnell micro-architectures do not support a number of modern instructions, such as SSE4 or AVX. Nonetheless, the upcoming AMD Jaguar micro-architecture will fully support not only SSE4, but also AVX, BMI and many other instructions, just like high-end Bulldozer/Piledriver cores.


Advanced Micro Devices recently disclosed to the GCC community how to enable support for its next-gen low-power micro-architecture code-named Jaguar, which the chip designer calls "btver2" internally. Based on the information released by AMD, the Jaguar low-power micro-architecture will support a set of instructions found in high-performance Bulldozer/Piledriver sores, including SSE4.1, SSE4.2, AES, PCLMUL, AVX, BMI, F16C as well as MOVBE.

It is necessary to note that execution of 256-bit AVX instructions requires either two 128-bit floating point units (FPUs) or one 256-bit FPU (or four 64-bit FPUs, which may not be the best solution). Considering the fact that Jaguar is a low-power/low-cost design, both options seem rather unlikely as are expensive to implement. Nonetheless, it is possible that AMD will change the design of Jaguar rather significantly compared to Bobcat and will move towards modular Bulldozer-like approach. In addition, Jaguar cores will be able to address 2MB of cache, not 512KB like Bobcat, which likely points to unified level-two (L2) cache of the new x86 core.

It is expected that Jaguar-powered Fusion accelerated processing units will sport improved performance thanks to higher IPC (instructions per clock), enhancements related to HSA (heterogeneous system architecture) and simultaneous operation of x86 and stream processing cores. Besides, the new Fusion APUs will integrate input/output controller, which will allow to make personal computers using just one highly-integrated system-on-chip.

AMD's Jaguar cores will be utilized inside code-named Kabini and Temash accelerated processing units and will be implemented using 28nm process technology. For low-cost/low-power systems AMD is developing code-named Kabini accelerated processing units, which features two or four Jaguar x86 cores as well as GCN graphics processing engine. For tablets and similar ultra low power applications, AMD preps APU known as Temash, which will also use Jaguar x86 core(s) and low-power graphics adapter.

AMD is expected to unveil more details about Jaguar in late August at Hot Chips conference.