AMD’s Roadmap Slide Does Not Predict Steamroller Cores in 2013

AMD Has No Steamroller APUs and CPUs for 2013 – Report

by Anton Shilov
11/05/2012 | 12:02 AM

The steam keeps going out of AMD as it continues to develop new products, but that does not mean that Steamroller-based accelerated processing units are due in 2013. Apparently, Advance Micro Devices plans to continue to use Piledriver cores with its code-named Richland APUs next year. Moreover, there are no new FX-series chips planned for 2013.

 

AMD has reportedly cancelled its code-named Kaveri chip with x86 Steamroller processing cores and will substiture it with code-named Richland accelerated processing unit with Piledriver x86 cores. The new chip will have new AMD Radeon stream processors, which will be presumably based on GCN (graphics core next) architecture. AMD’s Richland will remain compatible with FM2 platforms, which points to similar thermal design option.

A slide published by Donanim Haber web-site also points out that AMD’s FX 8300/6300/6300-series code-named Vishera processors will continue to be AMD’s top-of-the-range desktop offerings in 2013.

Steamroller x86 cores – which will power AMD's future  high-performance Opteron and FX chips – will be located inside dual-core modules and therefore processors on their base should be similar by design with Orochi and Viperfish, with some minor exceptions that will not be truly important (new memory controller, different internal buses additional tweaks, etc) for x86 performance. The main improvements will be independent instruction decoders for each core within a module, better schedulers, larger and smarter caches, more register resources and some other enhancements.

One of the reasons why dual-core Bulldozer modules [the same may be said about Piledriver] are not completely efficient  is because they have only one instruction decoder for two ALUs and one FPU. With steamroller, AMD not only incorporated two decoders per module, but also increased instruction cache size (to lower i-cache misses by 30%), enhanced instruction pre-fetch (the number of mis-predicted branches is down by 20% compared to Bulldozer ) as well as improved max-width dispatches per thread by 25%. AMD believes that Steamroller will provide 30% improvement in ops per cycle.

AMD also advanced single-core execution by implementing 5%-10% more efficient scheduling, incorporated higher-capacity register files and performed some other tweaks. It should be noted that while integer pipes of Steamroller will not be too different from existing ones, the floating point pipe will be a bit redesigned. In general, AMD promises that both integer and floating point per-core performance of Steamroller will be higher than they are today with Bulldozer micro-architecture.

One of the interesting features of AMD Steamroller will be its ability to disable unused parts of L2 cache. Since not all apps are cache-bound, this may result in decreased power consumption and/or AMD's ability to boost clock-speeds of its microprocessors dynamically.

 AMD did not comment on the news-story.