by Anton Shilov
11/19/2013 | 11:25 PM
At the Supercomputing Conference 13, Intel Corp. revealed form-factors and memory configuration details of the CPU version of the next generation Intel Xeon Phi processor (code-named "Knights Landing"), which is expected to ease programmability for developers while improving performance.
Historically, various accelerators – such as those based on FPGAs or graphics processing units – came into the form of add-on cards. When Intel Corp. first introduced its Xeon Phi co-processors, it also produced them in PCI Express card form-factor. However, thanks to the fact that Intel’s Xeon Phi are x86 compatible, they can run operating systems and can also work as central processing units. Intel Corp. has just confirmed that the future Xeon Phi will be available as standalone chips.
During the supercomputing conference (SC13), Intel unveiled how the next generation Intel Xeon Phi product (code-named "Knights Landing"), available as a host processor, will fit into standard rack architectures and run applications entirely natively instead of requiring data to be offloaded to the coprocessor. This will significantly reduce programming complexity and eliminate "offloading" of the data, thus improving performance and decreasing latencies caused by memory, PCI Expressed and networking.
Knights Landing will also offer developers three memory options to optimize performance. Unlike other Exascale concepts requiring programmers to develop code specific to one machine, new Intel Xeon Phi processors will provide the simplicity and elegance of standard memory programming models.
Intel Xeon Phi “KNL” socket-based products will come with high-bandwidth in-package memory buffers that will provide boost to memory-bound workloads and will also in-pacakge DDR memory buffers. Being compatible with standard DDR3/DDR4 platforms, Xeon Phi “KNL” will also greatly support workloads that demand a lot of memory.
According to a slide from an Intel presentation that leaked to the web earlier this year, Intel Xeon Phi code-named Knights Landing will be released sometimes in late 2014 or in 2015. The chip, which will be made using 14nm process technology, will come in either PCIe co-processor card or CPU form-factor. The KNL co-processor will support new AVX 3.1 instructions, built-in DDR4 memory controller, on-package high-speed memory and a number of other innovations.
The most important aspect about the Xeon Phi “Knights Landing” product is its performance, which is expected to be around or over double precision 3TFLOPS, or 14 – 16GFLOPS/w; up significantly from ~1TFLOPS per current Knights Corner chip (4 – 6GFLOPS/w). Keeping in mind that Knights Landing is 1.5 – 2 years away, three times performance increase seem significant and enough to compete against its rivals. For example, Nvidia Corp.’s Kepler has 5.7GFLOPS/w DP performance, whereas its next-gen Maxwell (competitor for KNL) will offer something between 8GFLOPS/w and 16GFLOPS/w.
Intel did not comment on performance numbers of the forthcoming product.