Intel plans to reveal some peculiarities of its dual-core processors, including dual-core Itanium-series processor designed for high-end servers, at IEEE International Solid-State Circuits Conference that begins today in
Intel Talks Dual-Core Itanium
Intel’s IA64 dual-core chip code-named Montecito is to be made using 90nm process technology and contain 1.72 billion transistors. The chip is expected to provide performance of up to 2.9 times higher compared to today’s top Itanium 2 processor, the 1.60GHz model with 9MB of cache. Still, the Montecito is projected to be a better power saver – at the same clock-speed it is claimed to consume 100W of power, 30W lower compared to contemporary flagship Itanium 2 product.
Montecito will be Intel’s first IA64 chip with two cores and 24MB of L3 cache. In 2003 Intel uncovered plans to implement its special “arbiter” bus into the chip code-named Montecito to manage how the cores collaborate between themselves, how they utilise their processor system bus and the L3 cache. No actual peculiarities of the design have been presented by Intel officials so far, but we can pre-suppose that the “arbiter” bus architecture may be utilised in all multiple-core CPUs from Intel that will come in future.
“Montecito will ship later this year and ramp to volume in 2006. We aren't providing specifics on a launch date,” Intel’s spokeswoman Erica Fields told X-bit labs.
At IDF Fall 2004 Intel Corp. demonstrated servers running Montecito processors.
Platform Peculiarities Yet to be Announced
“We aren’t providing many details on the peculiarities of the [new server] platform [just yet]. We have said that it is planned for 2.0GHz and will include Foxton (performance boosting technology), Vanderpool (virtualization technology), Pellston (reliability technology) and Demand Based Switching (power feature),” Ms Fields said.
The Montecito and
Intel’s Itanium 2 chips with two processing engines are expected to work using 667MHz Quad Pumped Bus and will feature Intel’s new core-logic for high-end servers code-named Bayshore. The latter is expected to provide support for DDR2 memory and PCI Express interconnection, bringing the latest innovations into the server market.