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ATI Technologies, Cadence Design Systems and TSMC announced that ATI’s first graphics processor that uses the so-called X Architecture interconnects have been made at TSMC. According to the companies, this is the first X-architecture chip ever produced at the Taiwanese foundry.

The X Architecture is a new approach to chip design whereby diagonal interconnects are employed to reduce chip costs, increase performance and lower power consumption. Targeted at chips with five or more metal layers, the X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees in relation to conventional orthogonal, or “Manhattan”, architecture. Layers one through three remain unchanged, preserving the design community’s investment in existing cell libraries, memory cells, memory compilers, datapath compilers, and IP hard cores. In addition, the X Architecture allows 45 degrees “wrong-way jogs”, which provides an additional four degrees of freedom in each layer of routing.

The X Architecture’s pervasive use of diagonal routing reduces wirelength by up to 20% and the via count by up to 30%, resulting in significant improvements in chip area, speed, power, and cost. In addition, the X Architecture’s wirelength reduction makes the routing problem 20% easier to solve, resulting in faster timing closure, improved reliability, and a reduction in signal-integrity problems, Cadence claims.

According to the statement sent to press, the ATI’s X-architecture chip is a “high-performance, high-volume PCI-Express graphics processor designed for desktop and notebook computers”. The ATI device was implemented using the Cadence X Architecture design solution and manufactured using TSMC’s 0.11-micron process. This implementation eliminated one metal layer from the original Manhattan design, reducing die costs. ATI did not reveal which graphics processor was made, but said the new device was expected to enter volume production late in the year.

To bring the X Architecture into manufacturing reality, TSMC created extensive test structures to formulate competitive X Architecture design rules and developed a unique OPC model and mask making techniques. TSMC also created enhanced technology files to handle diagonal design rules and parasitic extraction.

Cadence X Architecture design solutions for TSMC’s 0.13 micron and 0.11 micron process nodes are now available to select customers under Cadence’s value-based business model. X Architecture solutions for TSMC’s 90nm and 65nm process technologies are currently under development.

“As the industry leader in advanced graphics and digital media processors, ATI has long been a pioneer in adopting new chip design technologies. Using the Cadence X Architecture design solution, we have been able to increase the performance envelope while reducing costs, providing new opportunities and possibilities within our PC and consumer businesses,” said Greg Buchner, vice president of Engineering at ATI.

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