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The year 2006 along with the forthcoming graphics application programming interface (API) from Microsoft is likely to become a milestone for the whole computer graphics industry, or, at least, designers of visual processing units (VPUs) say so.

“2006 year is going to be a milestone year for the entire graphics industry,” said Nadeem Mohammad of S3 Graphics in an interview with X-bit labs

The representative for S3 Graphics seems to be correct, as next year Microsoft plans to release its new API that will unleash further boundaries for programmable pixel and vertex shaders and will unify them, making it easier for developers to program. Since the introduction in 2001, pixel and vertex shaders used totally different commands. One of the outcomes of such shift is introduction of graphics processors with unified pixel and vertex processors by market leaders ATI Technologies and NVIDIA Corp. But S3 Graphics says it had investigated such a possibility before the next-generation API specs were even thought about.

“This architecture for this new [Destination] generation has been in development quite a while, originally as part of our advance research group. This was well before any engagement in Microsoft on the DirectX 10 specification. I cannot comment on any of the features or specification of this product family. I will say that I am personally very excited about this design – it will have features and capabilities which I have dreamed about since my first work on graphics processors back in 1987!” Mr. Mohammad said.

Both ATI Technologies and NVIDIA Corp. agree that the future architectures should have unified pixel and vertex processors (even though in the past the latter was sceptical about the technology), which will spur further innovation in their functionality and catalyze development of more photorealistic games. But NVIDIA says that development of a graphics processor with load balancing between pixel and vertex shaders requires very good knowledge about balancing of performance so that there were not competition for the resources within the chip.


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