The first chipset for x86 multiprocessor servers from Intel code-named Twin Castle will change the market of core-logic devices for multiprocessor servers and will also modify Intel’s approach for core-logic development, according to sources close to Intel Corporation.

Intel’s chipset code-named Twin Castle for the upcoming generation of Intel Xeon MP processor code-named Potomac will be Intel’s first chipset for multiprocessor applications as well as the company’s initial attempt to create a core-logic with separate Memory Bridge and North Bridge chips.

The Twin Castle consists of three chips: TNB (North Bridge, PSB controller), XNB (Memory Bridge, connects TNB to memory channels) and ICH5 (I/O controller). One of the reasons why Intel made decision to create a chipset with separate memory and PSB controllers could be the company’s plans to develop a very flexible core-logic that could sport numerous types of processors as well as memory.

One of the main goals for Intel’s servers division is unification of components intended for use with Xeon and Itanium series processors. Although fully-compatible platforms for Itanium and Xeon CPUs are not expected to emerge in the foreseeable future, numerous components, such as memory controllers, could be used on both IA32 and IA64 platforms. What Intel needs is to develop enough building blocks and reference designs to allow system makers to compose server solutions according to their requirements. Currently Intel allows customers to pick up necessary I/O components, while core-components cannot be selected according to demand for certain features.

IBM already ships platforms based Summit chipsets that are compatible with both Itanium and Xeon processors: depending on platform and other conditions the company selects core-logic components and deploys them as a solution. Such approach greatly saves time as well as R&D expenses and Intel confirmed earlier this year it would roll-out a similar core-logic for IA32 and IA64 processors at some point.

Another goal Intel has to address is support for various types of memory. Nowadays memory technologies are developing pretty rapidly and to implement a new memory type chipset companies have to redesign their North Bridges, perform thorough testing and then certify the new platform. Given that Intel needs to deploy faster technologies as soon as possible, the firm is very likely to simplify the process of implementing faster flavours of random access memory. One of the ways to do this is to detach memory controller into a separate chip. Another positive outcome of such move would be decreased complexity of North Bridge.

One of the key technologies in Intel’s roadmap is FB-DIMM. FB-DIMM is a new memory interconnect technology standard for high-end memory connections. FB-DIMM transitions the memory channel to a serial interface and replaces the DIMM register with a memory buffer. FB-DIMM connections are expected to enable systems to scale the number of memory channels available to a server system. Implementations of FB-DIMM enabled DDR-II memory are expected in future Intel’s code-named Lakeport chipsets. At some point FB-DIMM will indisputably find home in high-end MP servers.

Intel remains silent about capabilities of its Twin Castle chipsets, but sources close to the company were already told the price of the so-called Twin Castle (Kit “A”) - $255 for three chips.