by Ilya Gavrichenkov
08/18/2008 | 05:14 PM
The HyperTransport Technology Consortium released the HyperTransport 3.1 specification today. The new specification extends the 2.6 GHz maximum clock speed of HyperTransport 3.0 released in 2006 to 3.2 GHz. This increase together with HyperTransport's double data rate (DDR) capability delivers up to 6.4 GigaTransfers/second (GT/s) per bit and yields aggregate performance of 51.6 gigabytes per second (GB/s) on a 32-channel link.
<%BANNER[article]%>HyperTransport is a high-bandwidth, point-to-point interconnect standard that provides the lowest latency for chip-to-chip, board-to-board and chassis-to-chassis links. The HyperTransport 3.1 specification defines three new clock rate steps of 2.8 GHz, 3.0 GHz and 3.2 GHz.
I would like to remind you that HyperTransport is primarily designed for AMD platforms. They use this bus to connect the CPU featuring an integrated memory controller with the chipset that also communicates with other system components including graphics cards. Therefore, HyperTransport bandwidth is one of the key characteristics of platforms on AMD processors. However, it is important to remember that top AMD CPUs available today and featuring HyperTransport 3.0 do not use its entire potential yet. This bus works only at 2.0 GHz maximum and is 16 bit wide, which provides peak bandwidth of 16 Gbytes/s. So, even without involving any new functionality AMD can easily increase the bandwidth of its processor bus.
Note that after today’s announcement, the maximum bandwidth of 16-bit HyperTransport bus reached that of 16-bit CSI bus. Intel is going to use this bus to connect its next generation processors on Nehalem micro-architecture with the chipset. However, looks like HyperTransport Technology Consortium competes not only against the upcoming Intel’s bus but also against PCI Special Interest Group that should introduce PCI Express 3.0 specification in 2009. The existing Express 2.0 spec runs at up to 5 GT/s and can deliver 16 Gbytes/s aggregate on a 16-channel link. The 3.0 version will handle up to 8GT/s and deliver up to 32 Gbytes/s.
Besides the new bus specification, HyperTransport Technology Consortium also announced a new HTX3 connector, a major enhancement to its HTX expansion connector specification. The HTX Connector specification defines the electrical and mechanical characteristics of an EATX motherboard interface connector, enabling CPUs to connect directly via a HyperTransport link to add-in card subsystems. New HTX3 solutions will benefit from the increased performance, flexibility and power management capabilities enabled by the new specification. In addition, backward compatibility preserves the value of existing HTX solutions. HTX3 supports up to 5.2 gigatransfers per second bandwidth (2.6 GHz clock rate), which more than triples the 1.6 gigatransfers per second bandwidth of the previous HTX specification (800 MHz). Moreover, support for link splitting enables designers to implement either one x16 link, one x8 link or two x8 links on a single connector. The ability to split one HyperTransport link into two allows the HTX subsystem to be connected to separate CPUs for better clustering performance and RAS support, a capability that is increasingly required by high-performance subsystems operating in multiprocessor designs.