Infineon Technologies and Micron Technology today announced the release of the complete specification for reduced latency DRAM II (RLDRAM II) architecture. Operating at speeds of up to 400MHz, RLDRAM II products are the second-generation,  high-speed double data rate (DDR) SDRAM that combines fast random access with extremely high bandwidth and high density targeting communication and data storage applications.

RLDRAM architecture is designed to meet the memory requirements of today's high-bandwidth communication applications. The device's eight-bank architecture is optimized for high speed and achieves a peak bandwidth of 28.8Gbps using a 36-bit interface and a 400MHz system clock. RLDRAM II boasts a low latency and random cycle time (tRC) of 20ns providing a higher data throughput. Additional advantages of the RLDRAM II feature set include; on-die termination (ODT), multiplexed or non-multiplexed addressing, on-chip delay lock loop (DLL), common or separate I/O and programmable output impedance and a power efficient 1.8V core. These features provide designers with increased design flexibility, balanced READ and WRITE ratio and the elimination of bus turnaround contention; as well as a simplified design-in process.

RLDRAM II devices are available in a standard 144-ball FBGA, 11mm X 18.5mm package to enable ultra high-speed data transfer rates and a simple upgrade path from former products. RLDRAM II devices are available in three configurations, 8Mx36, 16Mx18 and a 32Mx9. Infineon and Micron co-developed the RLDRAM architecture, ensuring standardization, multi-sourcing, and functional compatibility.

Both companies state that they continue to see more and more support for RLDRAM across the industry from various companies with various requirements.