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OCZ Technology Group and DataSecure LLC today announced the joint support of a new Posted Precharge and ultra low latency DRAM technology.

Posted Precharge is a novel feature to provide an effective workaround for the limited number of open pages in current DRAM technology. Through a series of minor die modifications, DataSecure’s Posted Precharge technology allows keeping memory rows open while accessing different pages in the same bank. If a secondary access to the same bank occurs, data are immediately available without the need of reopening the memory page. Through the integration of SRAM registers it is further possible to reduce CAS latency to warrant quasi-isochronous data access on read commands.

“Posted Precharge is a revolutionary concept to avoid bus contention and allow multiple open pages within the same bank of memory” commented G.R. Mohan Rao, one of the founders of DataSecure LLC.

“Especially in server applications with a high percentage of random accesses and in HyperThreading situations, posted precharge will allow not only recurrent accesses to the same page while maintaining superb bandwidth, but also opening the next page before the minimum bank cycle time is satisfied, which has been a major performance problem in any non-streaming application.”

“This is a significant step ahead of the autoprecharge and similar concepts currently in vogue.” added Dr. Michael Schuette, a cofounder of DataSecure LLC.

OCZ Technology did not say when those technologies are expected to be available in mass quantities on devices intended for end-users.

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