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Infineon Technologies said this week it had completed internal testing of its buffer chip intended to serve in fully-buffered DIMMs when they are available throughout the next couple of years.

The Infineon’s advanced memory buffer (AMB) test chip implements for the first time the crucial high-speed input/output stages together with other high-speed functionality such as the data-insertion and data-forwarding circuits in Infineon’s own logic process technology. The FB-DIMM standard foresees a data multiplexing by a factor of six to higher speeds to reduce the physical width of the memory channel and to minimize the throughput latency. The Jedec standard defines a maximum required datarate per IO pin of 4.8Gb/s for DDR2 800MHz. Infineon’s AMB test chip already runs at 6.0Gb/s, giving substantial system margin and ensuring lowest bit-error rates, the company said.

FB-DIMM is a new memory interconnect technology standard for high-end memory connections. FB-DIMM transitions the memory channel to a serial interface and replaces the DIMM register with a memory buffer. FB-DIMM connections are expected to enable systems to scale the number of memory channels available to a server system. Implementations of FB-DIMM enabled DDR-II memory are expected in future Intel’s chipsets, such as Glenwood and Lakeport.

”The new fully-buffered technology, with a specification standardized in JEDEC (Joint Electronic Device Engineering Council), provides an excellent opportunity to simultaneously increase both the speed of the DIMMs and the memory capacity on server platforms. FB-DIMM will also offer a smooth transition from DDR2 to DDR3 DRAM generations. This has the real potential to be an important new server memory technology in 2006 and onwards,” said Tom Macdonald, Vice President and General Manager of the Advanced Chipset Division at Intel.

Engineering samples of the FB-DIMM for DDR2 DRAM are planned to be available in the fourth quarter of 2004, market introduction is planned for the second half of 2005, Infineon said.

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