Elpida Memory announced that it has shipped samples of its Fully-Buffered Dual in-line Memory Modules (FB-DIMM) to its server partners for testing. The announcement confirms commitment of memory makers to the emerging standard and may mean that Elpida is on-track to produce FB-DIMMs in 2005.
Volume Production – in Late 2005
The initial samples shipped by Elpida are currently being used to test next-generation server platforms. Elpida Memory plans to offer FB-DIMM products in 2GB, 1GB and 512MB densities. The availability of engineering samples and volume production will likely begin during the second half of 2005, pending the availability of FB-DIMM-compliant memory controllers from third parties and the ratification of the JEDEC standard. Elpida did not say when commercial FB-DIMMs emerge.
The industry standard Fully-Buffered DIMM specification is complete and will be confirmed by JEDEC, Elpida said. FB-DIMMs have been designed to provide significant performance gains over current Registered DIMM solutions, and they will offer speeds up to 4.8Gbps data rate, equivalent to 6.4GB/s data bandwidth, two times more than existing DDR2 Registered DIMMs, which offer 3.2GB/s bandwidth.
Samsung Electronics also recently announced FB-DIMMs sampling.
FB-DIMMs – The Way to Go for Servers
Elpida’s FB-DIMM utilizes JEDEC-standard DDR2 SDRAM. However, the module design is completely new: in the FB-DIMM, all signals – clock, address, command and data – to and from the DRAM on the module are buffered at the high-speed Advanced Memory Buffer (AMB) chip located on the DIMM. This helps to secure the DRAM timing margins during high-speed operation with a much shorter signal path between the DRAM and the AMB.
The FB-DIMM also adopts a Point-to-Point connection on the bus between the memory controller and the DIMM, as well as between the DIMMs themselves. This allows increased bus speed with a shorter connection path. It also greatly improves the maximum number of DIMMs that can be loaded on the bus - up to eight 2-rank DIMMs - with less concern about signal degradation.
By comparison, existing standard Registered DIMMs have a stub-bus architecture along the memory bus between each DIMM and the memory controller. As the memory frequency increases, the controller must reduce the number of DIMMs loaded on the memory bus to secure the signal quality and the timing margin along the lengthy signal path between the DRAM devices on the module and the controller on the motherboard. Therefore, Registered DIMMs that provide 3.2 GB/s bandwidth (PC2-3200) are limited to four 1-rank DIMMs, or two 2-rank DIMMs. This limitation has presented a bottleneck in achieving improved performance in server applications where both high-speed and high-capacity are essential.
As processor speeds continue to increase, and as the server architecture changes, FB-DIMMs will be required to support next-generation server platforms.