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Micron Technology announced it could increase clock-speed of its Fully-Buffered DIMMs up to 667MHz, enabling future servers with higher memory bandwidth. The appropriate memory modules are tested by the company now and are expected to go into mass production sometime in the first half of 2006.

Micron Tests FB-DIMMs at 667MHz

“FB-DIMM and DDR2-667 is the key technology combination for high-density, high-performance memory required in next-generation bandwidth-intensive server applications. These products will begin to appear in production systems in 1H06, and Micron will be ready with a full array of FBDIMM products for server, workstation, and other market segment applications,” said Terry Lee, Executive Director of Advanced Technology and Strategic Marketing for Micron’s System Memory Group.

Micron Technology already demonstrated prototypes of its FB-DIMM products, but at lower clock-speed. The company says now it has a comprehensive lineup of FB-DIMMs for commercial production with densities from 256MB to 2GB. The firm’s Fully-Buffered Dual in-line Memory Modules with 667MHz memory chips are currently tested.

Other leading makers of memory chips and modules, such as Samsung Electronics and Elpida Memory, are also testing FB-DIMMs these days.

FB-DIMMs – The Way to Go for Servers

FB-DIMMs utilizes JEDEC-standard DDR2 SDRAM. However, the modules’ design is completely new: in the FB-DIMM, all signals – clock, address, command and data – to and from the DRAM on the module are buffered at the high-speed Advanced Memory Buffer (AMB) chip located on the DIMM. This helps to secure the DRAM timing margins during high-speed operation with a much shorter signal path between the DRAM and the AMB.

The FB-DIMM also adopts a Point-to-Point connection on the bus between the memory controller and the DIMM, as well as between the DIMMs themselves. This allows increased bus speed with a shorter connection path. It also greatly improves the maximum number of DIMMs that can be loaded on the bus - up to eight 2-rank DIMMs - with less concern about signal degradation.

By comparison, existing standard Registered DIMMs have a stub-bus architecture along the memory bus between each DIMM and the memory controller. As the memory frequency increases, the controller must reduce the number of DIMMs loaded on the memory bus to secure the signal quality and the timing margin along the lengthy signal path between the DRAM devices on the module and the controller on the motherboard. Therefore, Registered DIMMs that provide 3.2 GB/s bandwidth (PC2-3200) are limited to four 1-rank DIMMs, or two 2-rank DIMMs. This limitation has presented a bottleneck in achieving improved performance in server applications where both high-speed and high-capacity are essential.

As processor speeds continue to increase, and as the server architecture changes, FB-DIMMs will be required to support next-generation server platforms.

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