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Samsung Electronics said it would discuss some general peculiarities of implementation of DDR3 SDRAM at the forthcoming JEDEX 2005 conference in addition to some other challenges the company and its industry partners face with leading-edge technology.

According to the company’s statement, Jon Kang, Senior VP of the Technical Marketing Group at Samsung Semiconductor and seven distinguished staff engineers from the company will speak at the 4th Annual JEDEX 2005 Conference and Exposition in San Jose, California, on March 31-April 1, 2005, on key design challenges facing the semiconductor industry in memory architecture, wireless network interfaces, memory performance, board assembly and chip packaging.

Particularly, Samsung’s representatives will talk about design considerations for the DDR3 memory subsystem as well as high-performance graphics and network types of memory. Being the only supplier of the GDDR3 memory used on high-end graphics cards for about a year, Samsung is on the forefront of high speed memory.

Samsung Electronics announced in mid-February it had made the world’s first 512Mb memory chip which complies to next-generation DDR3 standard and can operate at the speed on 1066MHz. The prototype operates at 1.5V and transfers data at the speed of 1066Mbps. Samsung says DDR3 memory will be made using 80nm process technology; at present the company uses 90nm for DDR and DDR2 SDRAM production.

Samsung cites market research firm IDC as saying that the first DDR3 DRAMs will be sold in 2006 and that the DDR3 will represent 65% of the entire DRAM market in 2009. At the same time, Intel Corp.’s initial plans included platforms supporting DDR3 memory in 2007.

In addition to micro-architectural advantages DDR2 memory brings over the original DDR memory, such as, On-Die Termination (ODT) as well as larger 4-bit prefetch, additive latency, and enhanced registers, the DDR3 features self-driver calibration and data synchronization.

It is unclear what exactly will be discussed at JEDEX 2005.

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