Since DDR SDRAM supports Early Command, the impact of the CAS Latency has been reduced compared to SDR SDRAM. When transfering a preceding read, the earliest possible point in time for the issue of the next read command was two clock cycles with SDR SDRAM (no early command). If the delay between the issue of the read and the start of the transfer (which is just the CAS Latency by definition) is only 2 cycles, you achieve uninterrupted data transfer because those two cycles before the end are enough to cover the delay of the CAS Latency. As long as you can stay in page, this is an ideal situation.
But with CL 3, the situation is worse because you get one cycle delay between every burst. The does not only increase latency by one clock cycle, but also reduces the usable bandwidth for SDRAM with CL 3. Every read command produced at least one clock cycle delay, even when accessing data in the same page!

What remains for DDR SDRAM is that this situation does not occur even when having high CL values (3, 4, 5 or even 6 with DDR2 or GDDR3). The next command can always be issued exactly CL clocks before the end of the previous one. It is just right in time :)
This means that the CL value is of less importance to DDR SDRAM. While there is still an impact on the latency when - for example - missing a page, the overal importance is far less than compared to SDR SDRAM. With DDR SDRAM, other timings like tRCD or tRP have increased influence in overal latency while the CL was _THE_ dominat latency setting for SDR SDRAM.

So, what to expect from a DDR SDRAM memory stick with CL 1.5? If it timings are 1.5-3-3-7 (CL, tRCD, tRP, TRAS), its absolute latency may be worse than 2.0-2-2-6. And even if it is 1.5-2-2-6, it won't be much faster than the same timing except CL 2.